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Author SHA1 Message Date
Samuel Pitoiset
fcb568a5d5 docs: add alpha-to-one features for RADV 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28434>
 2024-04-01 10:50:52 +00:00
Samuel Pitoiset
f463901983 radv: advertise extendedDynamicState3AlphaToOneEnable with ACO 
PS epilogs aren't supported with LLVM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28434>
 2024-04-01 10:50:52 +00:00
Samuel Pitoiset
850605eba1 radv: advertise alphaToOne 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28434>
 2024-04-01 10:50:52 +00:00
Samuel Pitoiset
e7206bcdb2 radv: implement alpha-to-one 
This was missing and it's useful for Zink.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28434>
 2024-04-01 10:50:51 +00:00
Eric Engestrom
a5f1f39bf7 docs/egl: various wording improvements 
Drop mention of the option for classic drivers, be clearer about which
options enable gles1 and 2+, mention that it's 2+ and not just 2, be
clearer when we say "main library" that we're talking about the EGL lib,
and some grammar fixes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28497>
 2024-04-01 10:33:09 +00:00
Eric Engestrom
57ceedfc3e docs: mesa also implements gles 3.0+ 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28496>
 2024-04-01 10:11:43 +00:00
David Heidelberg
28a1cdf7e0 docs: we support EGL 1.5 for a long time 
Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28495>
 2024-04-01 09:52:36 +00:00
Iago Toral Quiroga
9fad2922fb broadcom/compiler: fix workaround for GFXH-1602 
In this scenario drivers are adding a dummy attribute with a size
of 1, so we should account for it here.

Fixes missing window decorations with GTK4+.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10853
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28414>
 2024-04-01 09:22:39 +00:00
Iago Toral Quiroga
ad647e2c90 v3d: implement fix for GFXH-1602 
Same fix as implemented for v3dv.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28414>
 2024-04-01 09:22:38 +00:00
Rohan Garg
3d68dd78d0 intel/eu/validate: Allow SIMD16 for mixed mode float operations on xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Rohan Garg
a368d234c8 intel/brw: Lower DWORD scattered read writes to lsc 
Rework:
 * Francisco Jerez: Rebase on 07b9bfacc7 ("intel/compiler: Move
   logical-send lowering to a separate file")
 * Jordan: Move SHADER_OPCODE_DWORD_SCATTERED_*_LOGICAL from previous
   patch, as it seems to make more sense here.
 * Jordan: Change `devinfo->has_lsc` ?: to if/else as suggested by idr

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Rohan Garg
b5040bfc3f intel/brw: Handle typed surface and atomic messages for xe2+ 
Reworks:
 * Francisco: Rebase on 07b9bfacc7 ("intel/compiler: Move
   logical-send lowering to a separate file")
 * Jordan: Rebase on 952a523abb ("intel: switch over to unified
   atomics")

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Francisco Jerez
74efde7663 intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*(). 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Francisco Jerez
f1812437e8 intel/eu/xehp+: Don't initialize mlen and rlen descriptor fields from lsc_msg_desc*(). 
These fields are overlapping with the ones set by brw_message_desc(),
so the latter should be used instead.  This fixes corruption of the
LSC message descriptors when inconsistent values are specified through
both helpers, which can happen if the 'inst->mlen' field is modified
during optimization (e.g. by opt_split_sends()).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Francisco Jerez
fa96274a87 intel/brw/xehp+: Replace lsc_msg_desc_dest_len()/lsc_msg_desc_src0_len() with helpers to do the computation. 
We cannot rely on the immediate message descriptor having accurate
values for mlen and rlen at the IR level, since they are updated at
codegen time via 'inst->mlen' and 'inst->size_written', which could
end up with values inconsistent with the message descriptor if
e.g. the split sends optimization had an effect.  Instead, define
helpers that do the computation without relying on the message
descriptor, and use the pre-existing
brw_message_desc_mlen()/brw_message_desc_rlen() helpers (fully
equivalent to the lsc helpers deleted here) during disassembly.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Ian Romanick
5f9ab41457 intel/brw/xe2: Update uniform handling to account for 512b physical registers 
Rework:
 * Jordan: Drop FINISHME (s-b Caio)
 * Jordan: Use reg_unit() in asserts rather than a ver check (s-b Caio)
 * Ian: Make use of reg_unit() in round_components_to_whole_registers()

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Ian Romanick
8587ef172c intel/brw/xe2: Update brw_nir_analyze_ubo_ranges to account for 512b physical registers 
Rework:
 * Jordan: Use `REG_SIZE * reg_unit` (Suggested by Caio)

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
 2024-04-01 00:00:03 +00:00
Faith Ekstrand
d5a8940812 nvk: Use a linked list for descriptor sets in a pool 
There's no real benefit to all this fixed size array nonsense.  We're
heap allocating all of the nvk_descriptor_set structs anyway so having
an array-of-pointers walk instead of a linked list is no faster.  Also,
this gets rid of another fixed-size array that can overflow.

Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28482>
 2024-03-31 20:42:59 +00:00
Faith Ekstrand
5c1683c9b9 nvk: Use a VMA heap for descriptor memory 
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28482>
 2024-03-31 20:42:59 +00:00
Faith Ekstrand
6cbd3a18d4 nvk: Use the page-aligned BO size for the descriptor pool 
The BO may have more space in it than requested since it's aligned to
64K. We may as well make that available to the client.

Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28482>
 2024-03-31 20:42:59 +00:00
David Heidelberg
a2d3cdd5f2 r300: add missing copyright header 
Missed copyright header in newly added file.

Fixes: 024491f60f ("r300: nir fcsel/CMP lowering pass for R500")
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28384>
 2024-03-31 13:03:01 +00:00
David Heidelberg
b2ae73b27e r300: add missing licence to the r300_public.h 
Hardly a copyrightable file, though it should inherit the MIT
license as the code originate from MIT licensed r300_winsys.h.

Fixes: 6e3fc2de2a ("r300g: Move bootstrap code to targets")
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28384>
 2024-03-31 13:03:00 +00:00
David Heidelberg
95eefce4d8 r300: convert to SPDX license block and fix small typos 
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28384>
 2024-03-31 13:03:00 +00:00
Marek Olšák
b6a93058b9 nir/opt_varyings: simplify nir_io_semantics::num_slots of directly-indexed slots 
Compaction only moves directly-indexed slots. This prevents unnecessary
num_slots > 1 from appearing in random slots.

Fixes: c66967b5cb - nir: add nir_opt_varyings, new pass optimizing and compacting varyings

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28431>
 2024-03-31 03:02:51 +00:00
Marek Olšák
71becd1b44 nir/opt_varyings: don't generate IO with unsupported bit sizes 
Backward inter-shader code motion turns ALU results into outputs,
which led to getting IO with unsupported bit sizes. This prevents
that.

There is a new NIR option flag that indicates 16-bit support.

Fixes: c66967b5cb - nir: add nir_opt_varyings, new pass optimizing and compacting varyings

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28431>
 2024-03-31 03:02:51 +00:00
Marek Olšák
5c543f4a02 tgsi_to_nir: translate TG4 
Tested-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28349>
 2024-03-30 22:25:19 -04:00
Timur Kristóf
96ee0d6711 ac/nir/tess: Remove dead code that was meant for epilogs. 
We no longer need to emit store_output intrinsics at the
end of the shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:51 +01:00
Timur Kristóf
b34e99d021 radeonsi: Use one more bit for number of patches in TCS offchip layout. 
There was 1 more bit left, may as well use it for something.
In the future, this may allow increasing the maximum number of
patches per workgroup.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:48 +01:00
Timur Kristóf
04dea4aef2 radeonsi: Remove tess bits from VS state. 
These parts are not used anymore, therefore we no longer need to
change the VS state when tessellation states change.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:45 +01:00
Timur Kristóf
b82614e06b radeonsi: Add number of VS outputs to TCS output layout. 
Use tcs_offchip_layout instead of VS state to determine the
number of LS outputs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:42 +01:00
Timur Kristóf
8883b88dd4 aco: Delete all TCS epilog code. 
Now that neither RADV nor RadeonSI uses TCS epilogs, we don't
need to keep the code to compile them in ACO either.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:39 +01:00
Timur Kristóf
078a23cde4 radeonsi: Delete TCS epilogs entirely. 
Always emit the tessellation factor writes in the main shader,
which is doable now that the necessary information is in the
tcs_offchip_layout SGPR.

This eliminates the need for TCS epilogs, so delete them
entirely from RadeonSI.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:35 +01:00
Timur Kristóf
71f9d4b9eb radeonsi: Implement dynamic TCS intrinsics for non-monolithic shaders. 
Put the primitive mode and whether TES reads tess factors into
the tcs_offchip_layout SGPR, so they can be used by the main
shader instead of needing the epilog.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:32 +01:00
Timur Kristóf
05dda3d6e7 radeonsi: Put HS output count in TCS offchip layout, not patch data offset. 
The intention is to free up enough bits in tcs_offchip_layout so
that it can contain information for more dynamic states.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:29 +01:00
Timur Kristóf
e68ab8651e ac/llvm, radeonsi: Handle tess_rel_patch_id in common code. 
We'll need to clean this up later, but for now it's better to
have it in common code than in RadeonSI.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:20 +01:00
Zan Dobersek
3ee81ffe14 tu: fix memory leaks in tu_shader 
When tu_shader object is destroyed through vk_pipeline_cache, the relevant
destroy callback should relay to the general tu_shader_destroy function
that will also clean up owned resources.

During shader creation, the ir3_shader object should be destroyed once the
shader variants are retrieved. Since those variants are owned by tu_shader
they should be freed up in tu_shader_destroy.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: a03525d8db ("tu: Split program draw state into per-shader states")
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27847>
 2024-03-30 08:56:03 +01:00
Alyssa Rosenzweig
fcf1a8062b asahi: switch to VS/FS prolog/epilog system 
With the exception of some variants for framebuffer fetch (to be addressed in a
follow up MR, this is big enough as it is) -- this switches us to a shader
precompile path for VS & FS. VS prologs let us implement vertex buffer fetch
with dynamic formats, FS prologs let us implement misc emulation like API sample
masking and cull distance, while FS epilogs handle blending and tilebuffer
stores. This should cut down shader recompile jank significantly in the GL
driver. It also prepares us with most of what we need for big ticket Vulkan
extensions like ESO, GPL, and EDS3.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:20 +00:00
Alyssa Rosenzweig
742a842811 asahi/clc: stop padding binaries 
we're going to switch away from the dynarray soon.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
3a2d13f59e asahi: add fast linker 
to stitch together programs from separate parts

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
66862fa160 agx: add main_size info 
so we can fastlink when there are preambles

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
0298c5d905 agx: add agx_shader_part data structure 
for fastlinking.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
e6105cdf0c asahi: static assert blend key size 
need to make sure it's padded because C

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
b0698b796e agx: drop shader stage assertion 
we'll reuse these for SW VS too which is HW compute

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
57fa9a2b8e nir: add intrinsics for non-monolithic agx shaders 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
99a4d0fcad asahi: don't allocate tib space for gaps 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
eadf4cfe1c asahi: constify agx_build_tilebuffer_layout 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
5d375e6143 asahi: add agx_usc_push_packed helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
9974f68bb9 agx: document non-monolithic ABI 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
a9ccd72265 agx: implement exports 
translate export/load_exported instructions into moves to/from the requested
GPRs at shader part boundaries, with coalescing in RA for perf.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00
Alyssa Rosenzweig
c6839cfd69 agx: generalize preloaded cache 
we'll need it for more regs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
 2024-03-30 00:26:19 +00:00