fbe8428af8
panvk/csf: Fix prepare_vp() when viewport->x is negative
...
The scissor descriptor wants positive min/max bounds.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31462 >
2024-10-02 15:51:34 +00:00
2203376865
panvk: Fix bounds checking in upload_shader_desc_info()
...
Replace the less-than test by a less-or-equal when checking the
dynamic buffer count.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31462 >
2024-10-02 15:51:34 +00:00
e489a92c33
panvk: Make sure RUN_IDVS has a valid tiler descriptor
...
As soon as we call RUN_IDVS, we need a valid tiler descriptor. Let's
kill the needs_tiling optimization until we have a proper way of
knowing when draws can be skipped or when IDVS jobs can be replaced
by plain compute.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31462 >
2024-10-02 15:51:34 +00:00
5b25784df7
zink+nvk/ci: document more flakes seen lately
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31483 >
2024-10-02 15:03:56 +00:00
6337bde12e
zink+nvk/ci: mark spec@egl 1.4@egl-ext_egl_image_storage as fixed
...
Fixed by a commit in the 27295ca4...d5df263a range
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31483 >
2024-10-02 15:03:56 +00:00
50f04a8e99
turnip/ci: mark vkd3d test_planar_video_formats as fixed
...
Fixed by a commit in the 765d1c47...366f63fd range, likely !31304
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31483 >
2024-10-02 15:03:56 +00:00
b8bfbbdf66
panvk: check against texfeat_bit
...
This is the same as the previous commit, but for PanVK instead.
Fixes: 213e895da0boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31419 >
2024-10-02 14:21:56 +00:00
6f1b5f3eea
panfrost: do not re-fetch compressed formats
...
We store this in the device on start-up, no need to do it again.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31419 >
2024-10-02 14:21:56 +00:00
23cad7c695
panfrost: check fmt.bitfeat_bit for compressed-support
...
Because we map compressed formats to the interchange-formats on V9 and
later, we end up not actually checking for compressed support here, but
instead always checking bit 0, which is reserved in the spec.
So let's instead explicitly check bitfeat_bit here instead, which we
conveniently stored away in the previous commit.
Use 1u instead of 1 for the shifted constant, to avoid undefined
behavior when we're testing bit 31.
Fixes: 0c1fde956bboris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31419 >
2024-10-02 14:21:56 +00:00
1637fa3d85
panfrost: store texfeat_bit in panfrost_format
...
To avoid increasing memory usage, make sure we pack this together with
the hw format.
This will be used in the next commit.
Fixes: 0c1fde956bboris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31419 >
2024-10-02 14:21:56 +00:00
8072c901e1
panfrost: unify compressed formats
...
This reduces some duplication, and we're going to start needing the
texfeat format on valhall anyway...
Fixes: 0c1fde956bboris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31419 >
2024-10-02 14:21:56 +00:00
d4fa181f7b
ci/image-tags: add DEBIAN_PYUTILS_TAG
...
Enforce maximum image tag length for DEBIAN_PYUTILS_TAG
and sort the tags in order.
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31475 >
2024-10-02 13:29:33 +00:00
30dc71b060
tu: Improve 2D buffer-to-image copies for A7XX
...
A7XX supports buffer-to-images copies with a lower alignment requirement
for the pitch and start VA, this makes it unnecessary to loop over every
row and copy them individually for any previously unaligned images. The
new alignment requirements match Vulkan requirements and should cover
all cases that aren't handled by 3D copies.
This can result in a significant performance improvement, up to 10x or
more in some cases.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31401 >
2024-10-02 12:56:40 +00:00
73e7ba8f14
freedreno/registers: Document TPL1_2D_SRC_CNTL register
...
This A7XX register is used for defining properties of the source buffer
for the 2D copies.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31401 >
2024-10-02 12:56:40 +00:00
61f3294786
pvr: unify code into one condition
...
gcc 13.2 incorrectly evaluate that first_use is unitialized value.
This should avoid the bug and make code clearner.
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Signed-off-by: David Heidelberg <david@ixit.cz >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31476 >
2024-10-02 12:16:19 +00:00
7702520239
radv: stop passing image create flags to radv_image_view_init()
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31463 >
2024-10-02 09:28:51 +00:00
e7cf039657
radv: remove redundant assertions about image views
...
The vulkan/runtime already has assertions.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31463 >
2024-10-02 09:28:51 +00:00
4308bf4cdf
radv: stop passing redundant parameters to radv_image_view_make_descriptor()
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31463 >
2024-10-02 09:28:51 +00:00
6bd9c4dad1
radv: use base mip level from vk_image_view
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31463 >
2024-10-02 09:28:51 +00:00
e76a26579a
radv/amdgpu: add assertions to check the IB size
...
This can be triggered with DGC if the maximum number of sequences count
is too high. Luckily, vkd3d-proton doesn't do that, but it should be
fixed for EXT DGC.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31464 >
2024-10-02 08:44:47 +00:00
d1f3a92671
radv/amdgpu: do not use a constant value for the IB size in dwords
...
Better to avoid magic number.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31464 >
2024-10-02 08:44:47 +00:00
816ae4ee67
ci/build: don't wait on the windows build anymore
...
Windows runners don't have more than one build right now, so there is
no need to wait on the "first one" to be done.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31473 >
2024-10-02 07:48:44 +00:00
f73d2eedfd
tu: advertise shaderInt64
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
38604485be
ir3: add support for 64b reductions
...
The existing scan/reduce macros (OPC_SCAN_MACRO/OPC_SCAN_CLUSTERS_MACRO)
hard code the reduction operations in ir3. Adding support for 64b
operations will blow up these already complicated macros. Implement a
simple scan loop in NIR for the few (hopefully rare) cases where the
generic passes cannot lower the reduction to 32b.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
52c456c641
tu: lower 64b push constants before lowering IO
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
8a17eb5377
ir3: make ir3_mem_access_size_align publically available
...
We want to reuse it from tu_shader.cc.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
aa9b8316ae
ir3: lower 64b SSBO accesses
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
c515d4bd81
ir3: run 64b phi lowering together with other 64b lowerings
...
nir_lower_64bit_phis was run in ir3_optimize_loop where it would fight
with nir_opt_if, causing shader compilation hangs. There's no point in
running this pass in the optimization loop as 64b phis should be lowered
together with the other 64b operations and then never appear again.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10355
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
ad12886775
ir3: lower 64b intrinsics after generic 64b lowering
...
ir3_nir_lower_64b_intrinsics will blindly set the def bit size to 32 for
unknown intrinsics. Give the generic passes a chance to lower them
first.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
4d50504b26
nir/lower_int64: add nir_intrinsic_rotate
...
Can simply be split into 32b ops.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Connor Abbott <cwabbott0@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
e6a5c342da
nir/lower_int64: add nir_intrinsic_read_invocation_cond_ir3
...
Can simply be split into 32b ops.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Connor Abbott <cwabbott0@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31455 >
2024-10-02 06:35:49 +00:00
584b63ecab
nir/load_store_vectorize: fix division by zero
...
Don't use glsl_get_explicit_stride as it may return 0 for vector types,
use nir_deref_instr_array_stride instead.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31460 >
2024-10-02 05:53:57 +00:00
366f63fd88
intel/brw: Enable mi_builder test for Xe2
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299 >
2024-10-01 16:03:35 -07:00
a0ea2a656f
intel/brw: Enable EU validation and compaction tests for Xe2
...
A few EU validation tests had to be updated to account for larger GRF,
extra supported types for 3-src instructions and the lack of AccWrEnable
in Xe2.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299 >
2024-10-01 16:03:35 -07:00
8b1c5425a9
intel/brw: Update DPAS validation tests for Xe2
...
The main change is that in Xe2 DPAS instruction requires SIMD16.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299 >
2024-10-01 16:03:35 -07:00
ee738c523a
isl/tests: split linear & tiled buffer sizes
...
There is this weird thing in the current tests that the linear & tiled
buffers are sized the same.
They don't need to be, compute a max area we want to check (aligned to
a tile logical size), allocate the linear buffer using that aligned
size and allocate the tiled buffer using a size aligned to the
physical tile size.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
d8da594a60
isl/tests: rename tile_(width|height) variables
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
05b641becc
isl/tests: add TileX memcpy testing
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
2994eca831
isl/tests: fix inclusive coordinate checking
...
The coordinates are supposed to be inclusive.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
0b22d43f86
isl/tests: use modulo for more variability per pixel
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
e80a02f52d
isl/tests: bump coordinate types to 32bits
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
451b9e6850
isl/tests: rename ytile to be consistent with other names
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
25d6b47298
isl/tests: fix coordinates for comparison scan
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
3384179e26
isl/tests: fixup multi-tile testing
...
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
86900e3cf6
isl/tests: add a space in memcpy test error printouts
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
b2b654d851
isl: fix comment typo
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469 >
2024-10-01 22:26:44 +00:00
b4acc3fc42
intel/brw: Remove Gfx8- from test_eu_validate.c
...
These tests only run for Gfx9+.
Acked-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31272 >
2024-10-01 21:16:54 +00:00
06dfcffd20
llvmpipe: correctly implement output variables loads
...
GLSL 4.60 spec, section 4.3.6: output variables
should behave like private variables during shader
execution. Framebuffer fetching now also checks
that fb_fetch_output is set on the variable.
cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31047 >
2024-10-01 20:28:00 +00:00
942a584db2
llvmpipe: fix quad group helper invocation masking
...
https://docs.vulkan.org/spec/latest/chapters/shaders.html#shaders-helper-invocations
Concretely, this fixes implicit derivatives of SSBO
variables on triangle edges, which are used in USD.
cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31047 >
2024-10-01 20:28:00 +00:00
8a1ce9a144
util/vbuf: delete/fix broken incompatible stride calc
...
this was accidentally duplicated from the conditional below,
except this one didn't have the buffer_stride_unaligned
caps check, which meant any 4-byte attrib which was
unaligned got marked for rewrites even on drivers
supporting unaligned strides
the correct change should have checked the stride against
the component size in the top case
Fixes: 7672545223marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31425 >
2024-10-01 19:52:02 +00:00
Boris Brezillon