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Author SHA1 Message Date
Arthur Huillet
f7d4e4ba2b nvk: import SPH headers files from open-gpu-doc 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29034>
 2024-05-16 07:56:30 +00:00
Chia-I Wu
a83c15654c drm-shim: intercept access as well 
Since libdrm commit 3bc3cca2 ("xf86drm: use drm device name to identify
drm node type"), drmGetMinorType uses access to get the node type and
causes amdgpu_device_initialize to fail with

  DRM_SHIM: unhandled core DRM ioctl 0x5 (0xc0286405)
  _amdgpu_device_initialize: amdgpu_get_auth (1) failed (-22)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29096>
 2024-05-16 07:18:14 +00:00
Karol Herbst
53629b0a2d rusticl: make use of new output_inline_wrapper meson.rust.bindgen feature 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25265>
 2024-05-16 06:40:59 +00:00
Karol Herbst
86a11248a5 rusticl: bump bindgen req to 0.65 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25265>
 2024-05-16 06:40:59 +00:00
Karol Herbst
c46cd101e1 rusticl: move mesa_version_string out of the inline wrapper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25265>
 2024-05-16 06:40:59 +00:00
Karol Herbst
d2dfb3350f rusticl: merge rusticl_nir and rusticl_mesa_bindings_inline_wrapper targets 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25265>
 2024-05-16 06:40:59 +00:00
Yiwei Zhang
2740d92e3d vulkan: drop redundant core props query and copy helpers 
The last client, venus, has stopped using those either.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
Yiwei Zhang
374a14ce4c venus: define VN_SET_VK_PROPS(_EXT) to simplify vk props init 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Reviewed-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
Oskar Viljasaar
3c152a6e5d venus: Use common physical device properties 
This lets us delegate the GPDP2 entrypoint to common code.
This also lets us delete struct vn_physical_device_properties,
as it is redundant with struct vk_properties present in the runtime.

Move the properties present in vn_physical_device_properties to the
local_devices struct used to query the host device properties, so we can
still get and fill those properties.

Replace accesses to struct vn_physical_device with accesses to
struct vk_properties filled in at device initialization time.

v2: rebase and a few fixups (zzyiwei)
- rely solely on vk props for final props sanitizations
- set vk11 props behind vk 1.2 condition
- set default pci props if forwarded
- set extension props based on extension support

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Reviewed-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
Oskar Viljasaar
f04bc27fe1 vulkan: add a property struct setter function 
This takes in a (VkBaseInStructure *), checks for its type, casts it
into the right property struct and then copies its fields over the right
way to `struct vk_properties`.

v2: a few fixups (zzyiwei)
- add missing brackets required by clang
- fix some indents
- optimize to aovid deep-copying VkPhysicalDeviceProperties
- update to use DETECT_OS_ANDROID as suggested
- cast to avoid -Wswitch for Android struct beyond VkStructureType

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
Yiwei Zhang
eb9a394e3c venus: move props sanitization to a separate helper 
So the main init properties function is clean. Also avoid giving any
sort of sane value for framebufferIntegerColorSampleCounts when we don't
query from 12 props directly, since the client side won't query that in
that case.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Reviewed-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
Yiwei Zhang
dceb1b0c4d venus: move custom props fill from GPDP2 to props init 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Reviewed-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
Yiwei Zhang
0197924d63 venus: directly use vk drm and pci props in renderer info 
We don't have to fill sType or pNext, and the default renderer info has
been zero-init already.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Reviewed-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
Yiwei Zhang
b1e2293f8c vulkan: cast to avoid -Wswitch for Android struct beyond VkStructureType 
Fixes: 1afbf0ba4a ("vulkan/properties: support Android in the property generator")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Tested-by: Oskar Viljasaar <oskar.viljasaar@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29180>
 2024-05-16 01:58:14 +00:00
David Rosca
c522848d5a radeonsi: Update buffer for other planes in si_alloc_resource 
The buffer is shared with all planes, so it needs to be updated
in all other planes. This is already done in si_texture_create_object
when creating the buffer, but it was missing when reallocating
in si_texture_invalidate_storage.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11155
Cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29216>
 2024-05-16 01:34:15 +00:00
Faith Ekstrand
ec90da3c76 nvk: Go wide for query copies 
There's no reason why we're doing a single invocation and a loop in the
shader.  We may as well let it parallelize on the off chance that
there's more than a few queries to copy.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29231>
 2024-05-16 00:49:08 +00:00
Faith Ekstrand
ce0da9ee97 nvk: Fix misc. whitespace and style issues 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29231>
 2024-05-16 00:49:08 +00:00
Roman Stratiienko
b0bba26f04 v3dv/android: Migrate ANB and AHB to use common helpers 
Change-Id: I28bfeaa93b2eacb353ea46e5e91cf2a2ae774067
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29059>
 2024-05-16 00:27:24 +00:00
Francisco Jerez
eebc4ec264 intel/brw/xe2+: Round up spill/unspill data size to nearest reg_size multiple. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:52 +00:00
Francisco Jerez
50daf161f4 intel/brw/xe2+: Lower 64-bit integer uadd_sat. 
Fixes failures of CTS tests that currently end up emitting 64-bit
integer ADDs with saturation, which isn't supported by the hardware.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:52 +00:00
Francisco Jerez
15a10786e3 nir: Add option to lower 64-bit uadd_sat. 
C.f. 16be909936.  Intel Xe2 won't
support saturation for 64-bit integer addition, regardless of
signedness.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
4bb5b25e53 intel/xe2+: Enable native 64-bit integer arithmetic. 
Note that some previously-supported 64-bit integer operations have
been removed from the hardware, so we need to instruct NIR to lower
them.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
8be9f00d84 intel/brw/xe2+: Lower 64-bit SHUFFLE and CLUSTER_BROADCAST. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
6261f4d361 intel/brw/xe2+: Fix 64-bit subgroup scan intrinsics not to rely on SEL instructions. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
1bf93ee4ec intel/brw/xe2+: Don't use SEL peephole on 64-bit moves. 
64-bit SEL isn't supported by the INT pipeline on this platform.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
b18e68fc25 blorp: Allocate fixed amount of space for blend state. 
According to the simulator a cacheline of the blend state cache
corresponds to 3 cachelines of L3 that are always filled regardless of
the number of render targets in use.  Allocate enough space to avoid
pagefaults under simulation, since a scratch page isn't bound by
default.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
b73638ae5e iris: Allocate fixed amount of space for blend state. 
According to the simulator a cacheline of the blend state cache
corresponds to 3 cachelines of L3 that are always filled regardless of
the number of render targets in use.  Allocate enough space to avoid
pagefaults under simulation, since a scratch page isn't bound by
default.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
8f798cc911 intel/brw/xe2+: Fix indirect extended descriptor setup for scratch space. 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
0d92ec44e5 intel/brw: Don't emit Z coordinate interpolation if CPS isn't in use. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Rohan Garg
475fb68726 intel/brw: We no longer have atomic fmin/fmax ops for fp64 in xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Rohan Garg
8d8d3666c6 intel/brw: Advertise fp64 atomic add's when we have 64 bit float support and a LSC 
Rework:
 * Lionel: Simplify to just checking ver >= 20.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez
7c129d9365 intel/brw/xe2+: Keep PS sample mask in the f1.0 register whether or not kill is used. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Rohan Garg
7668de019b intel/eu/xe2+: Fix src1 length bits of SEND instruction with UGM target. 
Rework:
 * Francisco Jerez: Specify the src1 length value in the correct
   units. Don't break earlier platforms.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Karol Herbst
f1662e9bc9 rusticl/mesa/context: flush context before destruction 
Drivers might still be busy doing things and not properly clean things up.

Fixes a rare crash on applicatione exits with some drivers.

Fixes: 50e981a050 ("rusticl/mesa: add fencing support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29223>
 2024-05-15 16:52:03 +00:00
Rohan Garg
ec06911b3d Revert "iris: slow clear higher miplevels on single sampled 8bpp resources that have TILE64" 
Miptails are now disabled on Tile64 resources, so we can drop this
restriction.

Ref: e3a5ade9 ('intel/isl: Disable miptails to align LODs for CCS WA')

This reverts commit 8670fd6ac4.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28984>
 2024-05-15 15:16:29 +00:00
Eric Engestrom
9e66d89be9 zink/ci: rename .zink-lvp-venus-rules to .zink-venus-lvp-rules to match the rest of the names 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29201>
 2024-05-15 14:34:56 +00:00
Iago Toral Quiroga
b545e78f12 v3dv: support 2712D0 
2712D0 has V3D 7.1.10 which included draw index and
base vertex in the shader state record packet, shuffling
the locations of most of its fields. Handle this at run
time by emitting the appropriate packet based on the
V3D version since our current versioning framework doesn't
support changes based on revision number alone.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29189>
 2024-05-15 13:57:10 +00:00
Iago Toral Quiroga
1fc846dce3 v3d: support 2712D0 
2710D0 has V3D 7.1.10 which included draw index and
base vertex in the shader state record packet, shuffling
the locations of most of its fields. Handle this at run
time by emitting the appropriate packet based on the
V3D version since our current versoning framework doesn't
support changes based on revision number alone.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29189>
 2024-05-15 13:57:10 +00:00
Iago Toral Quiroga
7b807c3e94 broadcom/cle: fix up shader record for V3D 7.1.10 / 2712D0 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29189>
 2024-05-15 13:57:10 +00:00
Lionel Landwerlin
0daf5e243f anv: shader printf example 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:38 +00:00
Lionel Landwerlin
5b76696861 intel/clc: enable printfs support 
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:38 +00:00
Lionel Landwerlin
64010716c8 anv: add debug shader printf support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:38 +00:00
Lionel Landwerlin
9a36278475 intel/nir: add printf lowering 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:38 +00:00
Lionel Landwerlin
6a8ff3b550 intel/compiler: store u_printf_info in prog_data 
So that the driver can decode the printf buffer.

We're not going to use the NIR data directly from the driver
(Iris/Anv) because the late compile steps might want to add more
printfs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:38 +00:00
Lionel Landwerlin
ecbec25e84 intel/nir: add reloc delta to load_reloc_const_intel intrinsic 
We'll use the delta for an upcoming internal printf mechanism, where
the PARAM_IDX will be the base printf reloc identifier and the BASE
will be the string id.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:38 +00:00
Lionel Landwerlin
dde91d18c2 intel/nir: remove unused prototypes 
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:37 +00:00
Lionel Landwerlin
c16e58eabd nir: add a low level printf emission helper 
Uses the same memory layout as the print intrinsic lowering. This one
just let's you do the emission without having to deal with variables.

This useful for debug traces.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:37 +00:00
Lionel Landwerlin
c518a176f5 nir: add ptr_bit_size parameter to nir_lower_printf 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:37 +00:00
Lionel Landwerlin
2be28ee58a nir: add a base offset for printf indexing 
This will allow a driver to use a single table of printf strings
across all shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:37 +00:00
Lionel Landwerlin
8d336f069e nir/divergence: add missing load_printf_buffer_address 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:37 +00:00