AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
191,541 Commits 1 Branch 0 Tags
f54dfbf4feb09497fa3acd18f0bd96e92d514ea4
Commit Graph

191541 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Caio Oliveira
f54dfbf4fe intel/brw: Move fs_reg data members up to brw_reg 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>
 2024-07-03 02:53:18 +00:00
Caio Oliveira
2ce6dcf043 intel/brw: Remove unused variable from test 
This would cause warning (and error in GitLab CI) after later changes to
fs_reg/brw_reg.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>
 2024-07-03 02:53:18 +00:00
Caio Oliveira
0d9f58db04 intel/brw: Remove RALLOC helper from fs_reg 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>
 2024-07-03 02:53:18 +00:00
Caio Oliveira
def70c1673 intel/brw: Remove unused brw_reg related functions 
Most of these were used by the vec4 backend that was removed from brw.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>
 2024-07-03 02:53:18 +00:00
Qiang Yu
8e146512d1 glsl: fix indirect tess factor access for compact_arrays=false drivers 
Driver with compact_arrays=false (i.e. radeonsi) is broken when
tess factor is accessed indirectly, for example:
  gl_TessLevelOuter[gl_InvocationID] = xxx;

This fix use nir_vectorize_tess_levels to lower array tess factor
access into direct vector access before nir_lower_io() like clip
and cull distance way.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29799>
 2024-07-03 02:06:56 +00:00
Qiang Yu
a071929f8d nir: consider more deref types when fixup deref 
Fix ANV and virpipe CI test fail when nir_fixup_deref_types
is used in nir_vectorize_tess_levels by later commits.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29799>
 2024-07-03 02:06:56 +00:00
Qiang Yu
f9ed3158b4 nir: nir_vectorize_tess_levels support indirect access 
Replace the implementation with nir_lower_array_deref_of_vec.

This will be used by compact_array=false drivers to lower indirect
tess levels array access to direct vector access too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29799>
 2024-07-03 02:06:56 +00:00
Qiang Yu
3151f5ec47 nir: add filter parameter to nir_lower_array_deref_of_vec 
To be used by latter commits to limit the lowering to specific
variables.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29799>
 2024-07-03 02:06:56 +00:00
Timothy Arceri
370ed7b021 glsl: make warning tests pass linking 
The standalone compiler previously ran these tests through a hacked up
partial linker. When this partial linker was recently removed from the
standalone compiler the --link option was turned on because some tests
are testing linking not just compilation. However in a future patchset
we will switch the standalone linker to use the nir linking code and
when this is done all of these shaders will need to pass full linking,
so here we update them to do so.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29991>
 2024-07-03 01:20:02 +00:00
Timothy Arceri
a71ce0a6d6 glsl: drop glsl ir optimisation from the standalone compiler 
There are no more users of the glsl ir at this point in the standalone compiler
anymore for these optimisations. Later patches will also switch the
standalone compiler to the nir linker.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29991>
 2024-07-03 01:20:02 +00:00
Timothy Arceri
063d62f142 glsl: move call to create explicit ifc layout out of glsl_to_nir 
We move this later so that we can call glsl_to_nir() on glsl ir that
has not set the array size on unsized ifc members. Later patches will
move sizing of the arrays out of glsl ir and into the nir linker.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29991>
 2024-07-03 01:20:02 +00:00
Jianxun Zhang
870be63c7e anv: Disable tracking of clear color on color attachment 
Xe2+ platforms don't need it because of its new fast-clear
and compression design.

Fixes: Vulkan CTS
dEQP-VK.pipeline.pipeline_library.multisample.
sample_locations_ext.draw.depth.samples_4.
separate_subpass_clear_attachments

src/intel/vulkan/anv_private.h:5439:
anv_image_get_fast_clear_type_addr: Assertion
`device->info->ver < 20' failed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29966>
 2024-07-03 00:55:13 +00:00
Jianxun Zhang
bd05ef9d91 anv: Support arbitrary fast-clear value on all layouts (xe2) 
Xe2+ platforms don't use fast-type buffer for its new design.
We don't have to track different fast-clear types, so we just
return the highest level of support.

Fixes: Vulkan CTS
dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image
_one_region.8_bit_not_all_remaining_layers

src/intel/vulkan/anv_private.h:5439: anv_image_get_fast_clear_type_addr:
Assertion `device->info->ver < 20' failed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29966>
 2024-07-03 00:55:13 +00:00
Jianxun Zhang
4034539c00 anv: Fix Vulkan CTS failure related to MCS (xe2) 
Fixes: Vulkan CTS
dEQP-VK.pipeline.monolithic.multisample.sampled_image.79x31_1.r32_uint.samples_2

src/intel/vulkan/anv_private.h:5439: anv_image_get_fast_clear_type_addr: Assertion
`device->info->ver < 20' failed.

deqp-vk: ../src/intel/vulkan/genX_cmd_buffer.c:1263: transition_color_buffer:
Assertion `must_init_fast_clear_state' failed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29966>
 2024-07-03 00:55:13 +00:00
Jianxun Zhang
beb0ea2469 anv: Disable tracking fast clear and aux state (xe2) 
Xe2+ doesn't use aux tracking buffers, and we should not
have access to the fast-clear type and compression state.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29966>
 2024-07-03 00:55:13 +00:00
Christian Gmeiner
01ea13cb6d etnaviv: isa: Extend disasm test 
With libetnaviv_parser we are able to parse the resulting string
representation into an etna_inst and assemble that to binary.

As we are not able to parse and/or assemble we need to mark some test
cases with special flags.

This allows us to test: bin -> disasm -> parsing -> assemble

If isa_parse_str(..) is not available we skip this part of the unit
test.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:55 +00:00
Christian Gmeiner
858d42bee9 etnaviv: isa: Add cli assembler 
Nothing too fancy.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:55 +00:00
Christian Gmeiner
6db922c0bf etnaviv: isa: Add C function impl 
Implement the following C API's:
 - isa_parse_str(..)
 - isa_parse_file(..)
 - isa_asm_result_destroy(..)

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:55 +00:00
Christian Gmeiner
d9bcaa1478 etnaviv: isa: Add parser module 
This commit adds the actual parser, which makes use of the IsaParser
derive proc macro.

It provides two public functions:
 - asm_process_str(..)
   Parse the provided isa representation and return an etna_asm_result.
   This will be used by our unit tests.

 - asm_process_file(..)
   Parse a whole file full of isa and return an etna_asm_result. This
   will be used by our cli assembler.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
db5e733e1b etnaviv: isa: Add EtnaAsmResultExt trait 
The impl of this trait provides some helpers to work with struct
etna_asm_result in Rust.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
0f93393cd6 etnaviv: isa: Make etna_asm_result usable in Rust 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
2ad2d86e49 etnaviv: isa: Add struct etna_asm_result 
This struct contains the result of an assembler run and will be filled
in Rust and consumed via a C API.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
863023ceda etnaviv: isa: Add IsaParser proc_macro_derive 
This proc derive macro does the following magic:
 - read static rules file
 - parse isaspec xml file
 - generate valid pest PEG grammar and attaches it as grammar_inline to
   the ast
 - calls pest_generator::derive_parser(..) to generate the parser
 - creates FromPestRule trait
 - creates FromPestRule impl for enums and opcodes

This is the fundation of our assembler.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
575814af14 etnaviv: isa: Add meson version check 
meson had an issue [1] with proc_macro that got fixed in 1.4.0 and newer.

[1] https://github.com/mesonbuild/meson/issues/12758

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
0ce255a9f6 etnaviv: isa: Make header C++ safe 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
15a784689e etnaviv: isa: Generate Rust FFI bindings for asm.h 
We will work with etna_inst_* structs in Rust.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
59406a9d85 etnaviv: isa: Add meta elements to instructions 
This commits adds a meta elements with the following attributes:
- has_dest: does the instruction has a dest register?

- valid_srcs: which sources need to be valid?
  Is used to generate PEST grammar and defines which of the three source
  registers needs to be != void.

- type: which <template> shall be used?
  Must match a known template name by the last part.
  E.g.: <meta type=tex"/> --> <template name="INSTR_TEX">

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
9e3e12e6a9 meson: Add indexmap rust dependencies 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
02bc51f477 meson: Add roxmltree rust dependency 
Will be used for a simple isaspec implementation in rust.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Christian Gmeiner
e28ff81869 meson: Add pest rust dependencies 
Including its dependency ucd-trie.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
 2024-07-03 00:07:54 +00:00
Mauro Rossi
87ad3ca0ac intel/common: fix building error in intel_common.c 
Fixes the following building error:

../out_src/src/intel/common/intel_common.c:29:4: error: implicit declaration of function 'free' is invalid in C99 [-Werror,-Wimplicit-function-declarat
ion]
   free(engine_info);
   ^
1 error generated.

Fixes: 5b8b4f78 ("intel/dev: Add engine_class_supported_count to intel_device_info")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29975>
 2024-07-02 23:35:26 +00:00
Jesse Natalie
74ba5cf885 blake3: fix Windows ARM64 build and detect ARM64EC as ARM64 
Cherry-picked upstream 0816badf3ada3ec48e712dd4f4cbc2cd60828278

Reviewed-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29971>
 2024-07-02 22:17:17 +00:00
Christian Gmeiner
3f91f2cf31 meson: Update syn subproject 
Fixes the following build error for fedora-release.

Error: method `inner` is never used
   --> ../subprojects/syn-2.0.39/src/attr.rs:589:8
    |
585 | pub(crate) trait FilterAttrs<'a> {
    |                  ----------- method in this trait
...
589 |     fn inner(self) -> Self::Ret;
    |        ^^^^^
    |
    = note: `-D dead-code` implied by `-D warnings`
    = help: to override `-D warnings` add `#[allow(dead_code)]`
error: aborting due to 1 previous error

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29996>
 2024-07-02 21:36:14 +00:00
Eric Engestrom
ab0956eec9 lavapipe/ci: skip timing out test 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30002>
 2024-07-02 21:20:47 +00:00
Mike Blumenkrantz
3d2d4f76d5 lavapipe: maint7 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29963>
 2024-07-02 21:06:13 +00:00
Iván Briano
9a68be59ca anv: enable VK_KHR_maintenance7 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29968>
 2024-07-02 20:24:43 +00:00
Iván Briano
53f196b8e0 vulkan/properties: handle LayeredApiPropertiesListKHR 
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29968>
 2024-07-02 20:24:43 +00:00
Samuel Pitoiset
384392d729 vulkan: Update XML and headers to 1.3.289 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29968>
 2024-07-02 20:24:43 +00:00
Jianxun Zhang
597c6cdf20 isl: Add some formats not covered in CMF table (xe2) 
The CMF values of these formats are not explicitly defined in the
spec. Refer to the added comment for more details.

Fixed Piglit tests:

[ISL_FORMAT_L8A8_UNORM_SRGB]
getteximage-formats -auto -fbo

[ISL_FORMAT_L8_UNORM_SRGB]
teximage-colors GL_SLUMINANCE8 -auto -fbo

[ISL_FORMAT_R9G9B9E5_SHAREDEXP]
fbo-generatemipmap-3d RGB9_E5 -auto -fbo

src/intel/isl/isl_genX_helpers.h:322: isl_get_render_compression_format:
Assertion `!"" "Unsupported render compression format!"' failed.

Also bump up Bspec revision in comments.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28620>
 2024-07-02 19:03:19 +00:00
Jianxun Zhang
77c83069ad intel/dev: Select a compressed PAT entry (xe2) 
Fix glxgears (LNL)

glxgears: xe/iris_kmd_backend.c:81: xe_gem_create:
Assertion `!"" "missing"' failed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28620>
 2024-07-02 19:03:19 +00:00
Jianxun Zhang
c9ee484f21 blorp: Ensure MSAA fast clear in correct modes (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28620>
 2024-07-02 19:03:19 +00:00
Ganesh Belgur Ramachandra
9c8dffd282 radeonsi: add GL_ARB_texture_filter_minmax extension 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29653>
 2024-07-02 18:27:00 +00:00
Ganesh Belgur Ramachandra
1f9bafbc74 radeonsi: add GL_EXT_texture_filter_minmax extension 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29653>
 2024-07-02 18:27:00 +00:00
Dylan Baker
11c27a6237 egl/wayland: fix memory leak in error handling case 
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29990>
 2024-07-02 17:45:12 +00:00
Jesse Natalie
137c506a7a subprojects: Use depth=1 in the git wrap files 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29361>
 2024-07-02 16:54:32 +00:00
Tim Huang
076cbf605e amd/vpelib: support VPE IP v6.1.3 
Use VPE_IP_LEVEL_1_0 for VPE IP version 6.1.3.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29930>
 2024-07-02 12:05:23 +00:00
Tim Huang
e322b2b683 amd: add GFX v11.5.2 support 
This is to enable GFX v11.5.2 support.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29930>
 2024-07-02 12:05:23 +00:00
Christian Gmeiner
9945f9e8d3 meson: Update proc-macro2 subproject 
There is a fix in 1.0.76 release that fixes an issue I have
seen on CI (fedora-release). Lets jump to the most recent
version 1.0.86.

See: https://github.com/dtolnay/proc-macro2/pull/435

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29992>
 2024-07-02 10:19:53 +00:00
Danylo Piliaiev
f77e9d8c4a ir3: Print bindless samp/tex ids for tex prefetch 
@tex(r0.z)  src=4, bindless=1, samp=4, tex=3, wrmask=0x7, opc=sam
@tex(r1.y)  src=4, bindless=1, samp=2, tex=1, wrmask=0xf, opc=sam

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29989>
 2024-07-02 08:16:02 +00:00
Juan A. Suarez Romero
c157e8991e v3d: use original enabled_mask on setting vertex buffers 
Current code uses a non-initialized enabled_mask to set the vertex
buffers mask, instead of using the original value from
`so->enabled_mask`

Let's use the original field instead of using an intermediate variable.

Fixes: cbcfb34cf7 ("v3d: use BITSET for the masks")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29987>
 2024-07-02 07:20:47 +00:00