356a60bd6c
anv: Do not duplicate intel_device_info memory in each logical device
...
Each logical device can point to its physical device intel_device_info
saving at least one intel_device_info.
This also allow us to set 'const' to avoid values in intel_device_info
being changed by mistake.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17897 >
2022-08-19 16:29:58 +00:00
f3b15143d2
intel: Simply intel_gem_create_context_engines()
...
We can use I915_DEFINE_CONTEXT_PARAM_ENGINES() to simply the filling
of engines_param.
As some compilers might not support VLA, defining struct with 64
engines, the maximum that i915 API supports.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961 >
2022-08-16 18:11:58 +00:00
1aeb11cde1
intel: protect against empty invalidate ranges
...
It's legal for an application to call vkInvalidateMappedMemoryRanges()
/ vkFlushMappedMemoryRanges() with zero sized ranges.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: b91971c240https://gitlab.freedesktop.org/mesa/mesa/-/issues/6852
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17481 >
2022-07-13 01:33:27 +00:00
6787c96039
intel/decoder: Use util_mask_sign_extend()
...
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17214 >
2022-07-06 11:23:18 +00:00
72e9843991
intel/compiler: Introduce a new brw_isa_info structure
...
This structure will contain the opcode mapping tables in the next
commit. For now, this is the mechanical change to plumb it into all
the necessary places, and it continues simply holding devinfo.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309 >
2022-06-30 23:46:35 +00:00
3dc6a98d78
intel/common: allocate space for at least one task urb
...
Fixes: c93cbc77f7lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196 >
2022-06-27 14:14:41 +00:00
f4386b81e6
intel: fix typos found by codespell
...
Acked-by: David Heidelberg <david.heidelberg@collabora.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191 >
2022-06-27 10:20:55 +00:00
a1a5f6430a
intel: provide a callback to clean up after intel_measure_gather
...
The caller may have passed ownership of intel_measure_batch structures
to intel_measure until they are ready to be gathered. The caller
needs a notification when rendering is complete and snapshots have
been processed, so it can free the resources that measure the batch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16571 >
2022-06-16 02:58:08 +00:00
c4c096e66e
intel: relax assertion in INTEL_MEASURE
...
It is possible that a secondary command buffer was submitted with no
renders in it. For that case, no timestamp will be collected. Only
verify that timestamps if the index is nonzero.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16571 >
2022-06-16 02:58:08 +00:00
3c53c6b247
intel: parse intel_measure environment without side effects
...
If an application links agaist both iris and anv, they will clash when
parsing the INTEL_MEASURE environment variable.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16571 >
2022-06-16 02:58:08 +00:00
60e29fc7c5
intel/gem: Add support for I915_ENGINE_CLASS_COMPUTE
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 >
2022-06-15 08:58:20 +00:00
ffb0c97caf
intel: Build mi_builder_test whenever build-tests is set
...
Previously `install-intel-gpu-tests` controlled this, but now
`install-intel-gpu-tests` will only be used to decide if it should be
installed.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16902 >
2022-06-07 18:26:02 +00:00
8381f64251
intel: Fix build of mi_builder_tests by including c99_compat.h
...
We need this so C++ will understand "restrict" which is used in the
genxml output.
Fixes: 9f717b5f23jordan.l.justen@intel.com >
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16899 >
2022-06-07 08:27:19 +00:00
b637f6c3db
intel/decoder: Fix binding table pointer decoding with large offsets
...
XeHP supports a 20:5 pointer format, so the offset can legitimately
be more than UINT16_MAX. Likewise, with 256B binding table mode on
Icelake/Tigerlake, we might have 18:8 pointers that exceed UINT16_MAX.
Thanks to Felix DeGrood for catching this!
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16538 >
2022-05-17 08:52:00 +00:00
b07c215c35
intel: fix URB programming for GT1s
...
We're missing a programming restriction.
Hopefully fixing
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.* on
Gfx9atoms
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6216
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >.
Tested-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15596 >
2022-04-17 21:24:17 +00:00
1407a4db69
intel/batch-decoder: Fix uninitialized scalar variables
...
CID: 1498516
CID: 1498560
Signed-off-by: Vitalii Lomaka <vitalii.lomaka@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15685 >
2022-04-08 18:35:34 +00:00
9bc97e4fc1
intel/decoder: Fix decoder handling of binding table pool alloc on XeHP
...
3DSTATE_BINDING_TABLE_POOL_ALLOC no longer has a "Binding Table Pool
Enable" bit. It is always enabled.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15625 >
2022-03-29 02:35:54 -07:00
3bd9b25060
intel: change INTEL_MEASURE output to microseconds
...
Change time event durations from ns -> us. Microseconds are easier
to work with.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
2e6d14cc7b
intel: increase INTEL_MEASURE batch/buffer sizes
...
Increase default batch_size and buffer_size from 16 -> 64. These
are sized to be big enough to service most games. As games have
become more demanding, larger sizes become necessary.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
12d815bcac
intel/guardband: Take min/max instead of total size
...
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14961 >
2022-03-16 13:13:45 -05:00
dbcdededb2
intel: Add missing dep of gen_*_header.py on utils.py.
...
Reviewed-by: Dylan Baker <dylan@pnwbakers.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725 >
2022-02-02 11:21:57 -08:00
c93cbc77f7
intel/common: Add helper for URB allocation in Mesh pipeline
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
b01c73fd0a
intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH
...
And corresponding value in XML.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
8599ded193
intel: Only reserve space for Compute Engine out of URB in Gfx12LP
...
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14756 >
2022-01-28 14:52:17 -08:00
79b199b333
intel: Allow copy engine class in intel_gem_create_context_engines()
...
I want to use I915_ENGINE_CLASS_COPY in iris.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687 >
2022-01-24 23:27:25 +00:00
695ba644ab
intel/gem: Return length from intel_i915_query_alloc
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13866 >
2022-01-19 00:29:35 +00:00
69df00b33b
intel/ds: reuse intel_ioctl()
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13996 >
2022-01-14 20:17:44 +00:00
14a4600b62
intel: add swizzle flag into driver uuid
...
Suggested by Lionel Landwerlin, we add has_bit6_swizzle as
another input when computing driver uuid.
Also fix miscalculation of the length of driver tag.
Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936 >
2022-01-13 03:09:36 +00:00
d86989bf73
intel: use PCI info to compute device uuid
...
With the new input from PCI bus and device fields, we can compute
device uuids in a multi-gpu system.
Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936 >
2022-01-13 03:09:36 +00:00
074bde9989
intel/xehp: Switch to coarser cross-slice pixel hashing with table permutation.
...
The coarser 32x32 cross-slice hashing mode seems to lead to better L1
and L2 utilization due to the improved execution locality, however it
can also lead to a bottleneck in a single slice, especially in
workloads that concentrate heavy rendering in small areas of the
screen (e.g. SynMark2 OglGeomPoint, OglTerrain*) -- This effect is
mitigated here by performing a permutation of the pixel pipe hashing
tables that ensures that adjacent rows map to pixel pipes as far away
as possible in the caching hierarchy.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
283d5bff4e
intel: Rename intel_compute_pixel_hash_table() to intel_compute_pixel_hash_table_3way().
...
For consistency with intel_compute_pixel_hash_table_nway().
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
170468b4fe
intel: Minimal calculation of pixel hash table for arbitrary number of pixel pipes.
...
This starts off with the simplest possible pixel hashing table
calculation that just assigns consecutive indices (modulo N) to
adjacent entries of the table, along the lines of the existing
intel_compute_pixel_hash_table(). The same function will be improved
in a future commit with a more optimal calculation.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
68cb551b1d
intel: Move pixel hashing table computation into common header file.
...
In order to avoid some duplication between the GL and Vulkan driver,
which will get worse as we introduce additional code in order to
handle more recent generations.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
fd2a558bf8
intel/l3: Make DG1 urb-size exception more generic
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14136 >
2021-12-11 00:09:50 +00:00
d051854cca
treewide: drop mtypes/macros includes from main
...
These aren't required in lots of places, so remove them.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14127 >
2021-12-08 22:14:45 +00:00
0634cb741b
intel: Add intel_gem_create_context_engines
...
Engines based contexts operate somewhat different for executing
batches. Previously, we would specify a bitmask value such as
I915_EXEC_RENDER to specify to run the batch on the render ring.
With engines contexts, instead this becomes an array of "engines", and
when the context is created we specify the class and instance of the
engine.
Each index in the array has a separate hardware-context. Previously we
had to create separate kernel level contexts to create multiple
hardware contexts, but now a single kernel context can own multiple
hardware contexts.
Another forward looking advantage to using the engines based contexts
is that the kernel does not plan to add new supported I915_EXEC_FOO
masks, whereas they instead plan to add new I915_ENGINE_CLASS_FOO
engine classes. Therefore some rings may only be usable with an engine
based class.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12692 >
2021-12-02 16:30:38 -08:00
9a9042a904
intel: Add intel_gem_count_engines
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12692 >
2021-12-02 16:30:31 -08:00
29c2f32a57
intel/dev: Add platform enum with DG2 G10 & G11
...
Based on Lionel's "intel/devinfo: store the different kind of DG2".
Ref: 361b3fee3chttps://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9e22cfc5e9b92556a56d8a564cdab31045f29010
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13797 >
2021-11-15 21:39:27 +00:00
361b3fee3c
intel: move away from booleans to identify platforms
...
v2: Drop changes around GFX_VERx10 == 75 (Luis)
v3: Replace
(GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
by
(devinfo->platform == INTEL_PLATFORM_IVB)
Replace
(devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
by
(devinfo->verx10 >= 45)
Replace
(devinfo->platform != INTEL_PLATFORM_G4X)
by
(devinfo->verx10 != 45)
v4: Fix crocus typo
v5: Rebase
v6: Add GFX3, ILK & I965 platforms (Jordan)
Move ifdef to code expressions (Jordan)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981 >
2021-11-08 16:48:06 +00:00
bba26939b1
intel/decoder: Dump Task/Mesh shaders
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13657 >
2021-11-04 21:01:13 +00:00
e69d395cd1
intel/genxml: Add an "mbz" data type
...
There are some fields which Must Be Zero, and we don't want to allow
setting them from the template struct, but we do want them in the XML
to allow them to be decoded properly, and for documentation purposes.
This adds a new "mbz" type, much like "mbo", except it doesn't set
anything in the struct. We also update the decoder to handle it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480 >
2021-10-28 19:45:55 +00:00
37f03e89f2
intel: Add and use max_constant_urb_size_kb
...
This knowledge was repeated in multiple places so move the values to
intel_device_info struct.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13014 >
2021-09-27 20:51:28 +00:00
929db0a818
intel/decode/gfx6: add support for gfx6 CC/VIEWPORT pointers.
...
These have 3 sub states encoded and valid fields on SNB.
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12864 >
2021-09-16 05:13:16 +10:00
18477f60e2
intel/dg2: Add L3 configuration
...
Rework:
* Jordan: Merge dg1/dg2 into empty_l3_list
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12711 >
2021-09-14 02:51:03 +00:00
ce1a66fe3e
meson/intel: Don't build genxml tests on Android
...
They require expat which we don't have on Android.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com >
Reviewed-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12308 >
2021-08-11 23:57:52 +00:00
e79a78a16f
intel/decode: add gfx4 vertex shader decode
...
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12160 >
2021-08-02 07:23:58 +10:00
0dec873f2a
intel/decode: add gfx4 constant buffer decode
...
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12160 >
2021-08-02 07:23:38 +10:00
b6843d990b
intel/tools/aubinator_error_decode: tag hanging instruction
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11957 >
2021-07-21 08:20:06 +00:00
f5008a48d3
intel/perf: Use intel_i915_query_flags instead of hand-rolling it
...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770 >
2021-07-16 14:19:20 +00:00
ffdf4d7683
intel: Pull anv_i915_query into common code
...
We also add a helper which contains the standard query+alloc+query
pattern used by anv_gem_get_engine_info(). The caller is required to
free the pointer.
These are declared static inline not because we care about the
performance of these helpers but because we're going to use them in the
intel_device_info code and we don't want a link dependency.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770 >
2021-07-16 14:19:20 +00:00
José Roberto de Souza