AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
208,612 Commits 1 Branch 0 Tags
f19e2e69e9ba179b15edc7cfa2f173842a70d103
Commit Graph

14247 Commits

Author SHA1 Message Date
Jordan Justen f19e2e69e9 anv: Set Xe3 as supported 
Backport-to: 25.1
Ref: 16a835ed3d ("anv: Drop "not yet supported" warning for Xe2")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31893>
 2025-07-14 18:53:48 +00:00
Valentine Burley 84923ccfe9 iris/ci: Lower concurrency of iris-cml-traces 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36074>
 2025-07-14 08:15:25 +00:00
Valentine Burley 2b50f93fb0 iris/ci: Add a performance traces job on ADL 
Add a new `iris-adl-traces-performance` job, which runs the same set of
traces as the `zink-anv-adl-traces-performance` job.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36074>
 2025-07-14 08:15:25 +00:00
Valentine Burley 7d298e3c4b iris/ci: Simplify performance trace template 
The `.profile-traces` template was nearly identical to
`.piglit-performance-base`, differing only by one additional variable.

Since all jobs extending `.piglit-performance-base` were already using
`EGL_PLATFORM: surfaceless`, that setting has been moved into the base
template, allowing `.profile-traces` to be simplified.

This also hides the performance traces jobs from non-Marge pipelines,
as intended.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36074>
 2025-07-14 08:15:25 +00:00
Sagar Ghuge 36172c41dc intel/compiler: Drop unused param from set_memory_address 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36092>
 2025-07-14 03:46:21 +00:00
Caio Oliveira 887642b0f2 intel: Add INTEL_DEBUG=no-vrt 
Add support for disabling the VRT (Variable Register Thread) feature.
The strategy here is to force the old BRW_MAX_GRF limit for the
register allocator (locks the upper limit) and make sure
ptl_register_blocks() always return that amount of blocks (locks
the lower limit).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35781>
 2025-07-13 21:11:02 +00:00
Yiwei Zhang b2a880b85e hasvk: adopt wsi_common_get_memory 
Similar to anv.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36095>
 2025-07-13 07:49:10 +00:00
Yiwei Zhang c647c422db hasvk: avoid leaking private binding for aliased wsi image 
This time for hasvk and is the same with
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35893

Aliased wsi image has to share the same private binding with the
original wsi image for memory consistency. If the private binding
exists, it needs to be released before being overridden.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36095>
 2025-07-13 07:49:10 +00:00
Yiwei Zhang 002235f64c anv: adopt wsi_common_get_memory 
It's non-trivial to drop the private binding or transfer ownership to
the bound memory. So we track the image in the device memory for
dedicated allocation so that wsi image alias can find the original wsi
image from the wsi memory.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36095>
 2025-07-13 07:49:09 +00:00
Sagar Ghuge e761c45390 anv: Set TG size based on number of threads 
Series shows improvement on
TotalWarPharaoh-trace-dx11-1440p-ultra-n=2080 title by 0.96% (not a lot
but still it's improvement, so will take that.)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35904>
 2025-07-10 22:08:36 +00:00
Sagar Ghuge 5f1f67358c blorp: Set TG size based on number of threads 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35904>
 2025-07-10 22:08:36 +00:00
Sagar Ghuge 0c4e1c9efc intel/common: Add helper for compute thread group dispatch size 
The recommended settings is just a guidance and not a programming
requirement as per the Bspec.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35904>
 2025-07-10 22:08:36 +00:00
José Roberto de Souza 59019a05f6 anv: Program DispatchWalkOrder and ThreadGroupBatchSize with optimized values for regular computer walkers 
It was only added to indirect compute walkers while HSD don't say
anything about this optimization be specific to indirect compute
walkers.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36058>
 2025-07-10 20:54:30 +00:00
José Roberto de Souza aea519cbc2 intel/blorp: Program DispatchWalkOrder and ThreadGroupBatchSize with optimized values for regular computer walkers 
It was only added to indirect compute walkers while HSD don't say
anything about this optimization be specific to indirect compute
walkers.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36058>
 2025-07-10 20:54:30 +00:00
Eric Engestrom 89403487b1 hasvk/ci: disable jobs on anholt farm 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36024>
 2025-07-10 18:15:36 +00:00
José Roberto de Souza 7aba9b3ebe anv: Decode and print async submit batch when debug flag is set 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35986>
 2025-07-10 16:21:05 +00:00
Ian Romanick 5adab50283 brw/nir: Use nir_opt_reassociate_matrix_mul 
This needs to be called before intel_nir_opt_peephole_ffma, so I
arbitrarilly decided to call it right before.

All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 17120227 -> 17118227 (-0.01%)
instructions in affected programs: 5854 -> 3854 (-34.16%)
helped: 51 / HURT: 0

total cycles in shared programs: 895497762 -> 894733940 (-0.09%)
cycles in affected programs: 4603518 -> 3839696 (-16.59%)
helped: 95 / HURT: 21

LOST:   1
GAINED: 0

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35925>
 2025-07-09 19:28:49 +00:00
Yiwei Zhang 374d97f24c hasvk: use AHARDWAREBUFFER_USAGE_CAMERA_MASK 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35785>
 2025-07-09 03:47:07 +00:00
Yiwei Zhang e394d29a75 hasvk: use common ANB swapchain gralloc usage query 
The usage bits issue probably isn't worth a separate backport for hasvk.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35785>
 2025-07-09 03:47:07 +00:00
Yiwei Zhang 4f80b14d0c anv: use AHARDWAREBUFFER_USAGE_CAMERA_MASK 
now that AHB header has it defined.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35785>
 2025-07-09 03:47:07 +00:00
Yiwei Zhang eb567fefc9 anv: use common ANB swapchain gralloc usage query 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35785>
 2025-07-09 03:47:07 +00:00
Yiwei Zhang 8f4c938c1e anv: fix ANB gralloc usage query to not append display usage bits 
The consumer of the Android surface may or may not be display. e.g. it
can also be a media encoder. When BufferQueue makes the allocation, it
takes the gralloc usage bits from both the client API (EGL/Vulkan) and
the consumer side.

Cc: mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35785>
 2025-07-09 03:47:06 +00:00
Sviatoslav Peleshko 8d22eb960b brw/disasm: Fix Gfx11 3src-instructions dst register disassembly 
The conversion from bit value to register file type is already done
by the brw_eu_inst_3src_a1_dst_reg_file in the FFC macro now, so doing it
again produced incorrect results.

Fixes: e7179232 ("intel/brw: Move encoding of Gfx11 3-src inside the inst helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13141
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35960>
 2025-07-08 19:49:09 +00:00
Daniel Schürmann 2c51a8870d nir: add nir_vectorize_cb callback parameter to nir_lower_phis_to_scalar() 
Similar to nir_lower_alu_width(), the callback can return the
desired number of components for a phi, or 0 for no lowering.

The previous behavior of nir_lower_phis_to_scalar() with lower_all=true
can be elicited via nir_lower_all_phis_to_scalar() while the previous
behavior with lower_all=false now corresponds to nir_lower_phis_to_scalar()
with NULL callback.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35783>
 2025-07-08 15:33:59 +00:00
Marek Olšák 8def3f865d agx,freedreno,intel,lima,panfrost,svga,virgl,zink: fix supports_indirect_inputs 
The GLSL compiler always lowers inputs to temps for VS and GS, so exclude
them from driver support because the GLSL compiler will no longer do that
unconditionally. Thus, indirect VS and GS inputs are completely untested
and broken in a lot of drivers.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35945>
 2025-07-08 06:11:42 +00:00
Lionel Landwerlin 67e452669e anv: do not rely on sampler objects for pipeline compilation 
Descriptor set layout lifetime can be shorter than what the
implementation requires. One example is :
  * create descriptor set layout
  * create graphics pipeline library
  * destroy descriptor set layout
  * link optimize library in a final pipeline

The last step might need the descriptor set layout information again.

We've so far worked around this by taking a reference on the
descriptor set layout in the pipelines. But we forgot that descriptor
set layouts have pointers to samplers (for immutable & embedded
samplers).

We could take a reference to samplers but that sucks for various
reasons :
  - it consumes dynamic state heap space
  - it could cause issues with capture-replay placement

So instead we copy the information from the samplers that might be
needed in cases like link optimization. This includes :
  - ycbcr conversion state (used for NIR lowering)
  - embedded sampler data (to recreate the sampler)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35955>
 2025-07-07 18:53:53 +00:00
Lionel Landwerlin 98bc185376 anv: rework embedded sampler hashing 
Create a hashing key on all samplers so we can just copy that anywhere
we need it. That key already contains the needed parameters for
embedded samplers, so the sha1 stuff can go away.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35955>
 2025-07-07 18:53:53 +00:00
Sushma Venkatesh Reddy fa0232d961 intel/executor: Add missing dependency to fix intermittent build failures 
The executor build was failing randomly due to a missing dependency on
`idev_intel_dev`. This patch adds the required dependency to the
`meson.build` file to ensure consistent and reliable builds across
different configurations.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35928>
 2025-07-07 18:35:56 +00:00
Sushma Venkatesh Reddy 29fc96cb80 anv: Add GPU breakpoint before/after specific compute dispatch call 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13089
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35353>
 2025-07-07 17:43:41 +00:00
Sushma Venkatesh Reddy 172e475705 intel: Add env variable to add break point on/before compute dispatch 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13089
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35353>
 2025-07-07 17:43:40 +00:00
Alyssa Rosenzweig d31cb824df treewide: use VARYING_BIT_* 
Via Coccinelle patch generated by the following Python:

  varys = [ "POS", "COL0", "COL1", "FOGC", "TEX0", "TEX1", "TEX2", "TEX3", "TEX4",
           "TEX5", "TEX6", "TEX7", "PSIZ", "BFC0", "BFC1", "EDGE", "CLIP_VERTEX",
           "CLIP_DIST0", "CLIP_DIST1", "CULL_DIST0", "CULL_DIST1", "PRIMITIVE_ID",
           "PRIMITIVE_COUNT", "LAYER", "VIEWPORT", "FACE",
           "PRIMITIVE_SHADING_RATE", "PNTC", "TESS_LEVEL_OUTER",
           "TESS_LEVEL_INNER", "PRIMITIVE_INDICES", "BOUNDING_BOX0",
           "BOUNDING_BOX1", "VIEWPORT_MASK", "CULL_PRIMITIVE" ]
  t = """
  @@
  @@

  -(1 << VARYING_SLOT_${V})
  +VARYING_BIT_${V}

  @@
  @@

  -BITFIELD_BIT(VARYING_SLOT_${V})
  +VARYING_BIT_${V}

  @@
  @@

  -(1ull << VARYING_SLOT_${V})
  +VARYING_BIT_${V}

  @@
  @@

  -BITFIELD64_BIT(VARYING_SLOT_${V})
  +VARYING_BIT_${V}

  """
  for v in varys:
      from mako.template import Template
      print(Template(t).render(V = v))

Closes: #13453
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> [panfrost, common]
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [broadcom]
Reviewed-by: Corentin Noël <corentin.noel@collabora.com> [virgl]
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> [zink]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35917>
 2025-07-04 19:01:04 +00:00
Mike Blumenkrantz 956d3f1562 mesa/st: handle renderbuffer with null zsbuf 
this matches cbuf handling

Fixes: 2eb45daa9c ("gallium: de-pointerize pipe_surface")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35941>
 2025-07-04 17:36:40 +00:00
Yiwei Zhang b21e62b71a anv: avoid leaking private binding for aliased wsi image 
Aliased wsi image has to share the same private binding with the
original wsi image for memory consistency. If the private binding
exists, it needs to be released before being overridden.

Fixes: d85a9d658f ("anv/image: Call into WSI to create swapchain images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35893>
 2025-07-03 17:40:31 +00:00
José Roberto de Souza 4830aec8ad anv: Reduce compiled code for Wa_16018063123 
Wa_16018063123 is not a workaround that depends on stepping, so we
can use the INTEL_WA_16018063123_GFX_VER macro to reduce code generate
for non affected platforms.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
 2025-07-03 14:09:13 +00:00
José Roberto de Souza 926e6a94ad anv: Do not emit batch_emit_fast_color_dummy_blit() for video engine 
Wa_16018063123 don't apply to video engine also video engine don't
support XY_FAST_COLOR_BLT.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Fixes: ec43c20182 ("anv: implement dummy blit for Wa_16018063123")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
 2025-07-03 14:09:12 +00:00
José Roberto de Souza 4618a99a4c anv: Flush before invalidate aux map in copy and video engines 
BSpec: 43904
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 46f5359238 ("anv: Invalidate aux map for copy/video engine")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
 2025-07-03 14:09:12 +00:00
José Roberto de Souza e68f81eaf6 anv: Read the correct register for aux table invalidation when in GPGPU mode in render engine 
For 3D or GPGPU modes the same render engine should be used, CCS
register should only be used when using compute engine.

Fixes: 46f5359238 ("anv: Invalidate aux map for copy/video engine")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
 2025-07-03 14:09:12 +00:00
Matt Turner 7da88c76db intel: Add support for BFloat16 as cooperative matrix accumulator 
The number of passing tests in ./deqp-vk -n '*cooperative_matrix.khr*'
on PTL increases from 914 -> 1030.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35320>
 2025-07-02 20:06:59 +00:00
Matt Turner e6242fb958 brw: Handle bfloat16 dest and src0 operands for DPAS 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35320>
 2025-07-02 20:06:59 +00:00
Caio Oliveira c006bee22d brw: Don't use simd_select for BS shaders 
Since there's only one possible SIMD, don't need to use
the helpers to decide which one to compile.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35799>
 2025-07-02 19:48:04 +00:00
Caio Oliveira c733f07378 brw: Use the right width in brw_nir_apply_key for BS shaders 
Fixes: 23c7142cd6 ("anv: disable SIMD16 for RT shaders")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35798>
 2025-07-02 15:32:23 +00:00
Lionel Landwerlin 343f3dd3c1 brw: fix non constant BTI accesses with offsets 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e103afe7be ("brw: run the nir_opt_offsets pass and set the maximum offset size")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35822>
 2025-07-02 01:04:06 +03:00
Iván Briano 5b58b838fe anv: move view_usage check to before setting the protected bit on it 
Otherwise the comparison will always be false for protected content.

Also remove extra setting of the protected bit that was happening later.

Fixes: 8d9cc6aa23 ("anv: properly flag image/imageviews for ISL protection")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35870>
 2025-07-01 21:40:44 +00:00
Sagar Ghuge 5f31e6b286 anv: Drop unused anv_rt_bvh_build_method enum 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35848>
 2025-07-01 20:00:35 +00:00
Lionel Landwerlin 89f3ee4cb2 brw: remove debug printf 
Fixes: fcf4401824 ("brw: handle wa_18019110168 with independent shader compilation")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35815>
 2025-06-29 12:39:03 +03:00
Calder Young 646977348b anv: Fix typo when checking format's extended usage flag 
Fixes: f4c1753c1a ("anv: report color/storage features on YCbCr images with EXTENDED_USAGE")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35703>
 2025-06-28 20:39:18 +00:00
Lionel Landwerlin a742b859bd anv: add support for handling wa_18019110168 with gfx-libs 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35103>
 2025-06-28 05:55:35 +00:00
Lionel Landwerlin fcf4401824 brw: handle wa_18019110168 with independent shader compilation 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35103>
 2025-06-28 05:55:35 +00:00
Lionel Landwerlin bc8d18aee2 brw: make a helper for vertex attribute offset computation 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35103>
 2025-06-28 05:55:34 +00:00
Lionel Landwerlin 8fabcd754f brw: move primitive_id_index field in fs_msaa 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35103>
 2025-06-28 05:55:34 +00:00