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Author SHA1 Message Date
Alyssa Rosenzweig
ee78628f78 pan/bi: Add bi_foreach_instr_and_src_in_tuple 
Rather specialized but keeps down obnoxious indentation in scheduler
passes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
a8fce919d2 pan/bi: Extract bi_ec0_packed helper 
Useful for scheduling decisions as well as packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
4252fb84f4 pan/bi: Add passthrough register rewriting helper 
Passthroughs are _required_ for correct scheduling, so we have to handle
this now. The legitimacy of using passthroughs is justified by the
constraint checks and verified with asserts at pack time.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
09c5d4ce18 pan/bi: Destructively schedule a single instruction 
Wrapper to select the best legal instruction, pop it off the worklist,
update the clause/tuple states, and return it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
63271dca9a pan/bi: Choose instructions to schedule 
In the future we'll want a heuristic minimizing register pressure but
for in-order this will suffice.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
a303076c1a pan/bi: Add bi_instr_schedulable predicate 
Using the previously defined checks for architectural scheduling
constraints, define one top-level predicate to check if an instruction
on the worklist is ready for scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
2537a53d5c pan/bi: Add writes_reg predicate 
ATEST is a bit of a wrinkle in this, so let's keep it in one place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
fb27baa35a pan/bi: Add T0/T1 constraint check 
Not visible on real shaders yet, but it will be when we schedule
out-of-order (or implement 64-bit multiplication).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
0349181e40 pan/bi: Validate reads_t 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
3f1cda5284 pan/bi: Add bi_count_succ_reads helper 
The number of register writes in a tuple must be bounded by a number
based on the number of register reads in the succeeding tuple, since
writes and reads are interleaved. This helper calculates that number of
reads, noting that not every read actually counts - if the preceding
tuple writes to a read source, that will become a temporary instead of
consuming a register slot.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
06bde2cc31 pan/bi: Add bi_tuple_is_new_src 
To determine the number of register reads in a tuple (which must be
bounded by 3, or 5 if you force writes), we need to count "new" sources:
those that are not already in a partially scheduled tuple.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
93c82c6fac pan/bi: Add FAU update helper 
This comes in destructive and nondestructive flavours, to be used to
insert an instruction into a tuple and check if an instruction is
insertable respectively. It is responsible for FAU slot matching.

It's annoying this sort of logic is duplicated in 3 places
(bi_lower_fau, here, and packing) but they each work with different sets
of assumptions...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
e5607c8745 pan/bi: Add constant count estimates to scheduler 
Needed to satisfy max constant constaints. These aren't precise but
they should be a good enough approximation for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
eb7e363688 pan/bi: Stub worklist routines 
In the near future we'll schedule out-of-order via a dependendency graph
and worklist. For now, emulate in-order operation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
3ddff0fa8b pan/bi: Flatten block lists 
From Midgard scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
39406571ec pan/bi: Add cubeface lowering 
For the new schedule infrastructure. This supports multiple tuples per
clause, unlike the old hack lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
7b4ab7bd2a pan/bi: Add scheduler data structures 
To satisfy the numerous architectural scheduler constraints, quite a bit
of state is required per-tuple, per-clause, and per-block. These data
structures allow maintaining this state separate from the main IR
data structures, allowing for partial constructions and nondestructive
operations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
07a3ccfbed pan/bi: Include ATEST datum in the instruction 
Rather than doing this at pack time like before, or adding extra
constraints to the already overcomplicated scheduler, let's just include
it like a regular FAU source.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
b8f042c9bb pan/bi: Dead code eliminate per-channel 
We already track the full liveness so this is a trivial optimization,
with an especial win for shaders reading only a subset of components of
gl_FragCoord.

More importantly, it's required for proper scheduling (in soft mode)
when vectors are used and some (but not all components) are promoted to
temporary registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
08d98290fe pan/bi: Cleanup terminal block check 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
4a27f8887d pan/bi: Print program size in shader-db 
Less critical than other metrics, but still matters for instruction
cache hit rate, and worth being aware of.

And, fine, it makes the scheduler look like a bigger win on another
axis.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Icecream95
6ecce71f71 pan/bi: Fix shader prefetch size 
The prefetch buffer size is larger than first thought, but includes
the final clause, so subtract the size of the final clause from the
prefetch size.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Icecream95
b5ab019b5a pan/bi: Return the size of the last clause from bi_pack 
Will be used for calculating prefetch size.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
 2021-02-08 14:07:29 +00:00
Alyssa Rosenzweig
b5c79e6d9f pan/bi: Lower transcendentals on G71 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
c4f26d12f9 pan/bi: Lower FP32 transcendentals where required 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
3aadebf4a8 pan/bi: Fix bi quirks detection 
There is no Bifrost v8...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
0219ecbfa0 pan/bi: Rename NO_FP32_TRANSCENDENTALS quirk 
Make it more obvious what the issue is. "_FAST" is not a suffix on
Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
0bdd4cbb57 pan/bi: Lower flog2 to a table and polynomial 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
d4c028f770 pan/bi: Lower FEXP2 with a table 
Connor's code, not the blob's, amusingly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
10b1f26687 pan/bi: Lower frsq to Newton-Raphson 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
c5e5d11599 pan/bi: Lower frcp to Newton-Raphson 
For G71 but should work on any Bifrost, probably overlaps some CL stuff.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
94fed29680 pan/bi: Fix FLOG_TABLE modifier handling 
These should not be in a union together.

[Note: this does not need to be backported, since the affected
instruction is not emitted under any circumstances in the stable
branches]

Fixes: dd11e5076e ("pan/bi: Add new bi_instr data structure")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Alyssa Rosenzweig
9157cf8124 pan/bi: Add bi_fmul_f32 convenience method 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
 2021-02-08 13:55:12 +00:00
Iago Toral Quiroga
8eeb61a3bf v3dv: add a perf trace when a device is created with robust buffer access 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>
 2021-02-08 13:00:16 +00:00
Iago Toral Quiroga
e6f8202749 v3dv: serialize pipeline compilation when debugging shaders 
It is possible to compile pipelines in multiple threads, but when we
are dumping debug information for shaders, we want all the outputs
serialized so we can make sense of it.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>
 2021-02-08 13:00:16 +00:00
Iago Toral Quiroga
44dcc4c24d v3d/common: use spaces instead of TABs 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>
 2021-02-08 13:00:16 +00:00
Erik Faye-Lund
ae8f9584f4 CI: always expose docs artifacts 
This makes it easier to preview docs changes in merge-requests. Also
make sure we build the docs right away, rather than waiting for when
marge merges. This allows us to see the artifacts right away.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8398>
 2021-02-08 11:39:10 +00:00
Samuel Pitoiset
6ac6e2fbfb radv: stop using VM_ALWAYS_VALID on APUs 
It seems that VM_ALWAYS_VALID means that all BOs must fit in
memory (VRAM+GTT) for each submission. This is causing a lot of
troubles when the total allocated memory is greater than the
available memory, especially on APUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8779>
 2021-02-08 11:24:25 +00:00
Samuel Pitoiset
6a3de3a31f radv: add radeon_winsys_bo::use_global_list 
This will allow us to use the global BO list even without
RADEON_FLAG_PREFER_LOCAL_BO which can cause a lot of troubles
on APUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8779>
 2021-02-08 11:24:25 +00:00
Karol Herbst
263bd5e6fd nouveau: print warning about unhandled cap only once 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8831>
 2021-02-08 10:52:32 +00:00
Samuel Pitoiset
0e00c4ea33 radv: use less AMDGPU contexts by creating only one per queue priority 
It should be more efficient. Suggested by Bas.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8878>
 2021-02-08 08:48:21 +00:00
Samuel Pitoiset
e498f25ff4 radv/winsys: stop zeroing radv_amdgpu_cs_request 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:49 +01:00
Samuel Pitoiset
abb3fab7c6 radv/winsys: remove unused fields in radv_amdgpu_cs_request 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:47 +01:00
Samuel Pitoiset
0856f559a9 radv/winsys: simplify the user fence logic for submission 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:46 +01:00
Samuel Pitoiset
05c383f948 radv/winsys: remove unused radeon_bo_usage enum 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:44 +01:00
Samuel Pitoiset
a6104ff053 radv/winsys: remove useless is_local check in radv_amdgpu_cs_add_buffer() 
radv_cs_add_buffer() already guarantees that and virtual buffers
are added via radv_amdgpu_cs_add_virtual_buffer().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:42 +01:00
Samuel Pitoiset
856775400d radv/winsys: remove useless continue preamble CS for IBs path 
It's only used for the sysmem path which is GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:40 +01:00
Samuel Pitoiset
e02b1577d0 radv/winsys: remove the radv_amdgpu_winsys_bo::ws indirection 
This saves a 64-bit pointer from radv_amdgpu_winsys_bo and it's
also common to pass a winsys pointer as the first parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:38 +01:00
Samuel Pitoiset
eb625b7a5f radv/winsys: use an array for the global BO list instead of a list 
This allows to remove one 64-bit pointer from radv_amdgpu_winsys_bo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:36 +01:00
Arcady Goldmints-Orlov
0b29a8a206 Revert "broadcom/compiler: improve generation of if conditions" 
This reverts commit 93f8f83a95.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8903>
 2021-02-08 06:52:59 +00:00