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Author SHA1 Message Date
Alyssa Rosenzweig ee671cf4f7 intel/nir_blockify_uniform_loads: use helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig 6b006db492 brw/nir_lower_storage_image: use helper 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig e3b6440b39 brw/nir_lower_shader_calls: use helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig ec8ed69131 brw/nir_lower_sample_index_in_coord: use helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig 544a739abc brw/nir_lower_fs_barycentrics: avoid nir_def_rewrite_uses_after 
replace is preferred when appropriate & should be faster. after is when
you use the result in your lowering itself.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:19 -04:00
Alyssa Rosenzweig 4fe8c19862 brw/nir_lower_alpha_to_coverage: eliminate goto 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:19 -04:00
Danylo Piliaiev 02138d96fd tu: Prevent GPU hang with occlusion query + certain depth state 
This state combination wedges something in GPU causing hang.
Forcing A6XX_LATE_Z prevents it. Prop driver does the same.

CC: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37765>
 2025-10-09 13:12:20 +00:00
Alyssa Rosenzweig c1d75c6e51 treewide: use BITSET_CALLOC 
Via Coccinelle patch:

    @@
    expression count;
    type T;
    @@

    -calloc(BITSET_WORDS(count), sizeof(T))
    +BITSET_CALLOC(count)

    @@
    expression count;
    type T;
    @@

    -calloc(sizeof(T), BITSET_WORDS(count))
    +BITSET_CALLOC(count)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37779>
 2025-10-09 12:29:55 +00:00
Alyssa Rosenzweig 85207a4f6a util: add BITSET_CALLOC helper 
comes up a bunch.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37779>
 2025-10-09 12:29:55 +00:00
Karmjit Mahil bb5f160dae freedreno/decode: Add 2d_to_json lua script 
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37677>
 2025-10-09 10:02:30 +00:00
Kenneth Graunke 73cbb35442 brw: Move into a new src/intel/compiler/brw subdirectory 
This keeps the directory structure a bit more organized:
- brw specific code
- elk specific code
- common NIR passes that could be used in both places

It also means that you can now 'git grep' in the brw directory without
finding a bunch of elk code, or having to "grep thing b*".

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:47 +00:00
Kenneth Graunke d1b0597213 brw: Drop compiler/ from brw includes 
They're in the current directory/module, just include them.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Kenneth Graunke af93215b7a intel: Re-unify brw_prim.h and elk_prim.h 
These are identical and are just hardware enum values, not related to
the structure of the backend compiler.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Kenneth Graunke d4c8ca43ef intel: Make a libintel_compiler_nir internal static library 
We were compiling these twice, one for brw, one for elk.  There's no
reason to do that, just compile the common code once and link against it
in both backends.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Kenneth Graunke 86aa241c66 brw: Rename brw_nir_trig build target to brw_nir_workarounds 
Matches the recent file rename.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Kenneth Graunke b15b83f43f brw: Drop ir_expression_operation_h from build system 
This is from the pre-NIR era where we used GLSL IR expression opcodes
directly.  We haven't done that in years.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Kenneth Graunke a7c2b87874 intel: Move intel_shader_reloc to common code and drop elk_shader_reloc 
We want to be able to emit load_reloc_const_intel intrinsics from common
NIR passes (such as printf lowering).  In order to do that, we need to
have the enum with the meaning of values in common code.  Once you have
that, it's easy to see the (identical) data structures as a way for the
driver to communicate about relocations, rather than a compiler backend
specific thing.  So we move it all up to common code, and re-unify.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Kenneth Graunke 116c65cd3d brw: Rename brw_shader_reloc to intel_shader_reloc 
In preparation for moving out of brw to common code.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Kenneth Graunke b458140b75 elk: Delete ELK_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH 
This is leftover brw code that nobody uses.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
 2025-10-09 07:01:46 +00:00
Rob Clark f448ad3adf freedreno/layout: gen8 descriptor support 
Add support to build gen8 descriptors.  The parameters/logic is largely
the same as a6xx/a7xx, but the layout is reshuffled.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:32 +00:00
Rob Clark ed6f0b982b freedreno/layout: Convert fd6_view to c++ 
The descriptor format changes for gen8, so we'll want a template param
to control which descriptors we build.

This also lets us drop the chip arg from fdl_view_args.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:32 +00:00
Rob Clark 344486d583 freedreno/a6xx: Slight re-org of sampler descriptor building 
A bit of re-org to make it easier to slot in the gen8 case.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:32 +00:00
Rob Clark 6195826826 freedreno/registers: pm4 updates for gen8 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:32 +00:00
Rob Clark 8a68c6684b freedreno/registers: Add gen8 descriptor layout 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:32 +00:00
Rob Clark 1d2895b232 freedreno/registers: Add gen8 regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:32 +00:00
Rob Clark 8edd6eb42e freedreno/registers: Common-ize PIPE definitions 
PIPE enum definitions are backward compatible. So move its definition
to adreno_common.xml.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark 6959bd9f54 freedreno/decode: Move enum lookup out of snapshot 
Some of these enums change between gens, which will be easier to deal
with if we move them out of the snapshot serialization helpers.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark d7db333b0e freedreno/decode: Add gen8 support 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark c1d1ba613b freedreno/registers: Extract out bitset for roq_avail 
De-duplication.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark 99b3283a5a freedreno/registers: Fix a couple reg names 
Fix typo in reg names.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark ed2e8d57e9 freedreno/registers: x_ADDR_MODE_CNTL is a6xx and earlier 
a5xx and a6xx could operate in either 32b or 64b mode (the former
untested upstream).  It appears that a7xx and later drop this back-
wards compat.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark 30e32c9c78 freedreno/registers: Rename some unknowns 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark 50ab38092f freedreno/registers: More register prep 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:31 +00:00
Rob Clark 67caa784cd freedreno/afuc: Add missing varset check 
Make sure afuc properly handles register variants.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:30 +00:00
Rob Clark f7ce548d78 freedreno/decode/crashdec: Limit snapshot BO size 
Internal tooling has a 100MB limit.  But ascii85 can do a good job of
compressing BOs that have lots of zero's, so the resulting snapshot file
can be much bigger than the devcoredump.  Avoid this by skipping BOs
that are large enough to probably not be cs/shader/descriptor.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:30 +00:00
Rob Clark 1a8a16f99d freedreno/a6xx: Move reg to static-non-context 
RB_UNKNOWN_8E09 is a non-context reg, we just need to set it and forget
it, so move it to static-regs.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
 2025-10-09 02:23:30 +00:00
Romaric Jodin cb86341829 meson: remove '--outdir' argument in script 
Usage of '--outdir' argument in python scripts makes it very
complicated for tools like ninja-to-soong to generate the Android
equivalent build file.
This is because the option is less clear on what will be generated.

Instead, change it for '--out' where we give the full path of the file
to generate. This has the good point of deduplicating the locations of
the file name to have it only in 'meson.build'.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37741>
 2025-10-08 20:51:20 +00:00
Lionel Landwerlin acf953757e brw: prevent LOAD_REG modifications on MOV_INDIRECT/BROADCAST 
Due to those opcode reading variable amount of data in src0, it's not
possible to easily figure out what builder SIMD size should be used to
produce the LOAD_REG replacement.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2d13acf9d9 ("brw: Add passes to generate and lower load_reg")
Fixes: 93996c07e2 ("brw: fix broadcast opcode")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14054
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37756>
 2025-10-08 20:17:22 +00:00
José Roberto de Souza a21b925caa anv: Rename anv_shader_bin to anv_shader_internal 
It is now only used by internal shaders to the rename make it more clear.

Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37749>
 2025-10-08 19:58:30 +00:00
José Roberto de Souza 5c8d7c30f5 anv: Simply anv_shader_set_relocs() parameters 
Now that we only have one caller for anv_shader_set_relocs() we can simply most
of parameter by struct anv_shader.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37749>
 2025-10-08 19:58:29 +00:00
José Roberto de Souza d5b8c7c17e anv: Drop shader relocs from anv_shader_bin_create() 
Acording to Lionel anv_shader_bin_create() is only used now for internal shaders
and those don't use relocs so we can drop this lines.

Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37749>
 2025-10-08 19:58:29 +00:00
José Roberto de Souza 62a746b353 anv: Replace duplicated code set shader relocs by a function 
This code was duplicated and with a assert mistake in one of the copies, so
here moving it to function and calling it from both places.

Also I have removed anv_shader_bin_rewrite_embedded_samplers() as it is already
being done in anv_shader_set_relocs().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37749>
 2025-10-08 19:58:28 +00:00
Yiwei Zhang 16458f756e ci/panfrost: udpate panfrost-g610-fails to reflect latest stats 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37776>
 2025-10-08 19:29:29 +00:00
Samuel Pitoiset aeec53f020 radv,radeonsi: use new ac_cmdbuf macros 
But keep them behind existing macros for consistency until all macros
are moved to common code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:15 +00:00
Samuel Pitoiset 902f5a8618 radv: replace radeon_cmdbuf by ac_cmdbuf completely 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:15 +00:00
Samuel Pitoiset 377f50129b radeonsi: replace radeon_cmdbuf_chunk by ac_cmdbuf 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:14 +00:00
Samuel Pitoiset 9ff4750eaf ac/cmdbuf: introduce ac_cmdbuf 
This will be shared by both drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:14 +00:00
Samuel Pitoiset a7ae26c96c ac/sqtt: use void pointers for start/stop CS 
Similar to BOs which are different structs between drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:14 +00:00
Samuel Pitoiset 12cccb2f75 radv: remove useless radeon_cmdbuf forwarded declaration 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:13 +00:00
José Roberto de Souza 379617b77d anv: Define bt_block only in the block that uses it in anv_cmd_buffer_alloc_binding_table() 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
 2025-10-08 17:26:42 +00:00