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freedreno/registers: Fix a couple reg names

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Fix typo in reg names.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
This commit is contained in:
Rob Clark
2025-09-18 15:04:21 -07:00
committed by Marge Bot
parent ed2e8d57e9
commit 99b3283a5a
4 changed files with 8 additions and 8 deletions
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src/freedreno/registers/adreno/a6xx.xml
+2 -2
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@@ -1990,8 +1990,8 @@ by a particular renderpass/blit.
<!-- 0x8e29-0x8e2b invalid -->
<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
<reg32 offset="0x8e3b" name="RB_SUB_BLOCK_SEL_CNTL_HOST"/>
<reg32 offset="0x8e3d" name="RB_SUB_BLOCK_SEL_CNTL_CD"/>
<!-- 0x8e3e-0x8e4f invalid -->
<!-- GMEM save/restore for preemption: -->
<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/>
src/freedreno/tests/reference/crash.log
+2 -2
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@@ -1548,9 +1548,9 @@ registers:
00000000 0x8e52: 00000000
00000000 RB_RBP_CNTL: 0
00000300 0x8e0c: 00000300
00000000 RB_RB_SUB_BLOCK_SEL_CNTL_HOST: 0
00000000 RB_SUB_BLOCK_SEL_CNTL_HOST: 0
00000000 0x8e3c: 00000000
00000009 RB_RB_SUB_BLOCK_SEL_CNTL_CD: 0x9
00000009 RB_SUB_BLOCK_SEL_CNTL_CD: 0x9
00000009 0x8e3e: 00000009
00000000 0x8e40: 00000000
00000000 0x8e41: 00000000
src/freedreno/tests/reference/crash_prefetch.log
+2 -2
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@@ -1763,9 +1763,9 @@ registers:
00000000 0x8e52: 00000000
00000001 RB_RBP_CNTL: 0x1
00010101 0x8e0c: 00010101
00000000 RB_RB_SUB_BLOCK_SEL_CNTL_HOST: 0
00000000 RB_SUB_BLOCK_SEL_CNTL_HOST: 0
00000000 0x8e3c: 00000000
00000009 RB_RB_SUB_BLOCK_SEL_CNTL_CD: 0x9
00000009 RB_SUB_BLOCK_SEL_CNTL_CD: 0x9
00000009 0x8e3e: 00000009
00000000 0x8e40: 00000000
00000000 0x8e41: 00000000
src/freedreno/tests/reference/prefetch-test.log
+2 -2
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@@ -2342,9 +2342,9 @@ registers:
00000000 0x8e52: 00000000
00000001 RB_RBP_CNTL: 0x1
00000101 0x8e0c: 00000101
00000000 RB_RB_SUB_BLOCK_SEL_CNTL_HOST: 0
00000000 RB_SUB_BLOCK_SEL_CNTL_HOST: 0
00000000 0x8e3c: 00000000
00000009 RB_RB_SUB_BLOCK_SEL_CNTL_CD: 0x9
00000009 RB_SUB_BLOCK_SEL_CNTL_CD: 0x9
00000009 0x8e3e: 00000009
00000000 0x8e40: 00000000
00000000 0x8e41: 00000000