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Author SHA1 Message Date
Alyssa Rosenzweig eda00fd39d pan/bi: Extract INSTRUCTION_CASE macro 
Useful across multiple optimization tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:23 +00:00
Alyssa Rosenzweig ffde1f359b pan/bi: Adapt bi_lower_branch for Valhall 
Disable the Bifrost optimization; it's not portable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:23 +00:00
Alyssa Rosenzweig f3937d9874 pan/bi: Trade off registers/threads on Valhall 
It's only v6 that's missing this feature.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:23 +00:00
Alyssa Rosenzweig 7637502c8d pan/bi: Add BI_SUBGROUP_SUBGROUP16 option 
Valhall uses 16-wide warps.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig ec9c1f8fa6 pan/bi: Wire Valhall disassembler into compiler 
Useful when we grow Valhall support (soon!)

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 31e991d801 pan/bi: Support standalone Valhall disassembly 
$ bifrost_compiler disasm --gpu=G78 foo.bin

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 600f689a98 pan/bi: Allow CSE of preloaded registers 
Needed to CSE `LEA_VARY` in varying shaders on Valhall.

No shader-db changes on Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 3154df232b pan/bi: Use a progress loop for constant folding 
Needed to fold the dependent patterns produced by texture instructions
during NIR->Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig e5582710f3 pan/bi: Mark NOP as having no destinations 
More accurate and more convenient.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 2604c65174 panfrost: Unify barrier+helper handling 
These are unified in the hardware, so let's unify them in pan_shader_info.
Hoisting this logic to pan_shader.c avoids the need to duplicate this logic for
Midgard/Bifrost (RSD packing) and Valhall (SPD packing).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 30d0c2e390 panfrost: Set texel_interleave on Valhall 
Instead of specifying the tiling on the texture descriptor, Valhall specifies it
on the plane descriptor. There is a new flag on the texture descriptor
specifying only whether the planes are interleaved or not.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 407bda4d8c panfrost: Adapt estimate_texture_payload_size to Valhall 
The plane descriptor is larger than earlier surface descriptors, so we need to
be somewhat careful here. This removes a memory micro-optimization in the
interest of simplifying the code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 469a36d071 panfrost: Don't emit compression tags on Valhall 
Unnecessary. To avoid even more #if/#endif soup, merge the v4, v5-v8, and v9
paths together -- by returning 0 as the compression tag on v4 or v9.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 087b63cb07 panfrost: Allow uploading fragment SPDs 
SPDs don't have the state dependence that fragment RSDs do.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig e42b0c68f4 panfrost: Don't pack blend constants with blend shaders 
It's probably harmless, but it is logically meaningless. The DDK doesn't do it,
I don't see a reason for us to, either. In theory this should be a small
overhead win.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 111f5af303 panfrost: Generalize some is_bifrost users 
Valhall would want these too. Regretting the is_bifrost check at all..

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 36a2b8d039 panfrost: Add PAN_MESA_DEBUG=dump option 
To dump all graphics memory via the new pandecode_dump_mappings function(),
since for Valhall I have to do this often enough to warrant a dynamic flag.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 28743a5556 panfrost: Rename prepare_rsd->prepare_shader 
This hook will be repurposed on Valhall to prepare the Shader Program
Descriptor, which takes the role of the RSD. Rename to avoid confusion.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 631c01fc42 panfrost: Add an enum for Valhall resource tables 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig f3c971e0fe panfrost: Make Divisor E an integer on v9 
For consistency with previous architecture's XML files. Logically this is an
1-bit unsigned integer, not a boolean.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig b19afaf307 panfrost: Clarify contains descriptor? bit 
Influences cache prefetching. I don't see a good reason to put anything other
than descriptors inside shader resources, meaning always setting this bit is
appropriate (at least for GLES).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 1df6b0d7e2 panfrost: Remove Invalidate Cache from Valhall job header 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 217e038289 panfrost: Add Tile Render Order enum to fragment jobs 
Not sure what this is needed for yet.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig 52ccd21e6b panfrost: Extend SPD size 
There is software-defined state at the end we don't need. Model in the XML for
correct behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
 2022-03-01 19:43:22 +00:00
Thong Thai 0136545d16 radeonsi: add check for graphics to si_try_normal_clear 
Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15177>
 2022-03-01 19:05:06 +00:00
Lionel Landwerlin 214092da87 anv: fix fast clear type value with external images 
Disable fast clear if not supported by the external modifier.

v2: Set fast_clear value to NONE in case of import/export from/to external

v3: Move logic next to existing acquire/release checks (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6056
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15096>
 2022-03-01 17:37:13 +00:00
Oleksandr Gabrylchuk 02fab4cf9e venus: Implement guest vram blob type. 
Add support of GUEST_VRAM type of blob. These are dedicated heap memory
allocations required for vk support on hypervisors that don't support
runtime injections of host memory into guest physical address space.

The flow of usage:
1) Host VM reserves dedicated heap memory
2) Device get info about memory reservations and report it to guest
using mmio registers
3) Guest virtio-gpu driver on starts checks mmio registers for
physical address and length of reserved region. Then it reserves it
in guest.
4) On each call of vkAllocateMemory() guest driver gets chunk of
required memory and send it to host using sg list. It uses one sg
entry for 1 blob call. Heap is managed on guest using drm memory
manager (drm_mm).

Signed-off-by: Oleksandr.Gabrylchuk <Oleksandr.Gabrylchuk@opensynergy.com>
Signed-off-by: Andrii Pauk <Andrii.Pauk@opensynergy.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14536>
 2022-03-01 17:25:56 +00:00
Marek Olšák fd3451babd amd: update addrlib 
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
 2022-03-01 17:03:00 +00:00
Marek Olšák f8cf5ea982 amd: add support for gfx1036 and gfx1037 chips 
Both are identified as GFX1036 for simplicity.

Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
 2022-03-01 17:03:00 +00:00
Marek Olšák 48046d5bd8 ac: set correct cache size per TCC for Yellow Carp 
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
 2022-03-01 17:03:00 +00:00
Samuel Pitoiset 4380916b76 radv: disable DCC for Fable Anniversary, Dragons Dogma, GTA IV and more 
Also Starcraft 2 and The Force Unleashed II.

These games are known to be affected by the feedback loop issue. We will
fix this properly soon but as a hotfix disabling DCC should be enough.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4424
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15203>
 2022-03-01 16:33:18 +00:00
Vadym Shovkoplias dc921f7377 iris: Do not apply SCANOUT allocation flags for SHARED-only requests 
It provides similar solution as in [1].

This was workaround for the users of gbm_bo_create_with_modifiers(),
which were unable to specify the buffer usage (GPU / GPU+DISPLAY).

But after the commit [2] this become possible. And forcing usage to
GBM_BO_USE_SCANOUT migrated directly into gbm_bo_create_with_modifiers
[3], allowing us to remove such workarounds from the drivers.

[1]: ef3b31c9 ("v3d: Don't force SCANOUT for PIPE_BIND_SHARED requests")
[2]: 268e12c6 ("gbm: add gbm_{bo,surface}_create_with_modifiers2")
[3]: ad50b47a ("gbm: assume USE_SCANOUT in create_with_modifiers")

Suggested-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5642
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14264>
 2022-03-01 16:04:44 +00:00
Timur Kristóf 93087f71e6 ac/nir: Extract final mesh shader output counts to a separate function. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
 2022-03-01 15:37:12 +00:00
Timur Kristóf 11957d3863 aco: Remove superfluous code for mesh shader workgroup ID. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
 2022-03-01 15:37:12 +00:00
Timur Kristóf 2d5aae032b ac/nir: Properly invalidate mesh shader metadata. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
 2022-03-01 15:37:12 +00:00
Timur Kristóf 3a3bd9cff1 ac/nir: Fix workgroup ID in mesh shader waves other than the first. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
 2022-03-01 15:37:12 +00:00
Timur Kristóf 57775dd76a ac/nir: Store mesh shader API and HW workgroup size in lowering state. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
 2022-03-01 15:37:12 +00:00
Timur Kristóf d0f45c7c49 ac/nir: Reuse existing nir_builder for emit_ms_finale. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
 2022-03-01 15:37:12 +00:00
Timur Kristóf 74f1e7965e ac/nir: Use vertex count minus 1 to determine max index in mesh shaders. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
 2022-03-01 15:37:12 +00:00
Charlie Turner 16b417b8d6 ci, valve: Add the dEQP runners for Valve CI 
v2.

  - Build the runner image as part of the CI for the boot2container
  project, rather than as a manually step using the build instructions
  in valve-trigger.dockerfile.

  - Depend on a non-default kernel build hosted in the valve-infra
  package repository. This does reduce the current caching feature of
  local artifacts, but makes it easier to chop and change kernels on a
  per-project or even per-test basis.

v3.

  - Depend on a kernel built and stored in the valve-infra generic
  package repo.

  - Build the runner container using ci-templates as part of the CI in
  valve-infra.

  - Now that the runner container is built in the valve-infra CI, I
  dropped the source import of client.py and message.py. They are
  built in the runner container.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
 2022-03-01 13:04:14 +00:00
Charlie Turner f0aee991bf amd, ci: Categorize the sections of the CI file. 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
 2022-03-01 13:04:14 +00:00
Charlie Turner 58186df32c amd, ci: Drop log level in SPIRV -> NIR code generator. 
See 786fa3435c for the rationale of this variable, but the point is to
avoid many error reports for conformance conformance issues within the
VK-CTS shaders.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
 2022-03-01 13:04:14 +00:00
Charlie Turner cc327a0fe4 amd, ci: Remove unused runners. 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
 2022-03-01 13:04:14 +00:00
Samuel Pitoiset 1e010348ee radv: remove color exports in presence of holes 
If there is holes, eg. if only MRT0 and MRT2 are exported, we have to
set MRT1 to SPI_SHADER_32_R to avoid a GPU hang but the export can
still be removed from the fragment shader.

fossils-db (Sienna Cichlid):
Totals from 565 (0.42% of 134913) affected shaders:
VGPRs: 13328 -> 11456 (-14.05%)
CodeSize: 613232 -> 548224 (-10.60%); split: -11.13%, +0.53%
LDS: 284672 -> 296960 (+4.32%)
MaxWaves: 17624 -> 17684 (+0.34%)
Instrs: 113056 -> 100445 (-11.15%); split: -11.68%, +0.53%
Latency: 684327 -> 639348 (-6.57%); split: -7.17%, +0.60%
InvThroughput: 122877 -> 104382 (-15.05%); split: -15.18%, +0.13%
VClause: 2601 -> 2323 (-10.69%); split: -10.77%, +0.08%
SClause: 5629 -> 5443 (-3.30%); split: -3.91%, +0.60%
Copies: 9393 -> 8720 (-7.16%); split: -8.22%, +1.05%
PreSGPRs: 14623 -> 13666 (-6.54%); split: -6.76%, +0.22%
PreVGPRs: 9847 -> 8503 (-13.65%)

fossils-db (Polaris10):
Totals from 565 (0.42% of 135960) affected shaders:
SGPRs: 28064 -> 27104 (-3.42%)
VGPRs: 12516 -> 10544 (-15.76%); split: -15.79%, +0.03%
CodeSize: 516920 -> 456536 (-11.68%); split: -11.68%, +0.00%
MaxWaves: 4369 -> 4418 (+1.12%)
Instrs: 97771 -> 85903 (-12.14%); split: -12.14%, +0.00%
Latency: 767482 -> 708545 (-7.68%); split: -7.97%, +0.29%
InvThroughput: 280017 -> 235744 (-15.81%)
VClause: 2270 -> 2090 (-7.93%); split: -8.50%, +0.57%
SClause: 5185 -> 5012 (-3.34%); split: -3.86%, +0.52%
Copies: 8328 -> 7555 (-9.28%); split: -9.35%, +0.07%
Branches: 1143 -> 1113 (-2.62%)
PreSGPRs: 13816 -> 12725 (-7.90%); split: -7.92%, +0.02%
PreVGPRs: 9707 -> 8270 (-14.80%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15108>
 2022-03-01 12:28:47 +01:00
Rhys Perry f800af2231 ac/nir: remove TCS nir_var_shader_out memory barrier 
nir_var_shader_out writes are only used for later TES invocations, so I
don't think there's any need for the TCS workgroup to wait for them.

fossil-db (Sienna Cichlid):
Totals from 1691 (1.04% of 162293) affected shaders:
Instrs: 710699 -> 709008 (-0.24%)
CodeSize: 3830168 -> 3823404 (-0.18%)
Latency: 3396997 -> 3007934 (-11.45%)
InvThroughput: 1212094 -> 1082823 (-10.67%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15195>
 2022-03-01 11:02:43 +00:00
Caio Oliveira 7460199a2f intel/compiler: Lower Task/Mesh I/O before SIMD specific lowering 
These are the same for all variants, so just lower it before cloning
the nir_shader for each of them.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15019>
 2022-03-01 07:35:13 +00:00
Danylo Piliaiev 549e861dc1 turnip: Implement VK_EXT_physical_device_drm 
Copied from ANV and V3DV.

v1. Fix a build error for clang "unannotated fall-through between switch labels"
( Hyunjun Ko <zzoon.ko@igalia.com> )

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6011

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14971>
 2022-03-01 07:10:40 +00:00
Pierre-Eric Pelloux-Prayer bb6ba8f21f radeonsi/drirc: use force_gl_vendor for Maya 
Otherwise OpenCL initialization fails with "unknown vendor id 0".

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15151>
 2022-03-01 07:43:26 +01:00
Ilia Mirkin d3196bac51 nouveau: add dEQP/GLCTS run failure info for GF108/GT215 
I happened to have these plugged in. Ran them against mesa 21.3 and
recent VK-GL-CTS tree (shortly after vulkan-cts-1.2.8).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14797>
 2022-02-28 22:36:31 -05:00
Nanley Chery dc05615ec1 Revert "anv: Require the local heap for CCS on XeHP" 
This reverts commit 382f6ccda8.

The spec requires that all color images created with the same tiling
(and a few other properties) support the same memoryTypeBits. So this
wasn't a valid change. It also wasn't necessary - we already have a
mechanism in anv_BindImageMemory2 for disabling compression if the BO
doesn't support it.

With this, XeHP passes the tests in
dEQP-VK.memory.requirements.*tiling_optimal

Fixes: 382f6ccd ("anv: Require the local heap for CCS on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
 2022-03-01 00:02:51 +00:00