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Author SHA1 Message Date
Samuel Pitoiset ec347ee9bc aco: fix combining add/sub to b2i if a new dest needs to be allocated 
The uses vector needs to be expanded to avoid out of bounds access
and to make sure the number of uses is initialized to 0.

This fixes combining more v_and(a, v_subbrev_co_u32).

fossilds-db (Vega10):
Totals from 4574 (3.28% of 139517) affected shaders:
SGPRs: 291625 -> 292217 (+0.20%); split: -0.01%, +0.21%
VGPRs: 276368 -> 276188 (-0.07%); split: -0.07%, +0.01%
SpillSGPRs: 455 -> 533 (+17.14%)
SpillVGPRs: 76 -> 78 (+2.63%)
CodeSize: 23327500 -> 23304152 (-0.10%); split: -0.17%, +0.07%
MaxWaves: 22044 -> 22066 (+0.10%)
Instrs: 4583064 -> 4576301 (-0.15%); split: -0.15%, +0.01%
Cycles: 47925276 -> 47871968 (-0.11%); split: -0.13%, +0.01%
VMEM: 1599363 -> 1597473 (-0.12%); split: +0.08%, -0.19%
SMEM: 331461 -> 331126 (-0.10%); split: +0.08%, -0.18%
VClause: 80639 -> 80696 (+0.07%); split: -0.02%, +0.09%
SClause: 155992 -> 155993 (+0.00%); split: -0.02%, +0.02%
Copies: 333482 -> 333318 (-0.05%); split: -0.12%, +0.07%
Branches: 70967 -> 70968 (+0.00%)
PreSGPRs: 187078 -> 187711 (+0.34%); split: -0.01%, +0.35%
PreVGPRs: 244918 -> 244785 (-0.05%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7513>
 2020-11-10 10:25:00 +01:00
Vinson Lee 7004548bdf turnip: Remove pipeline NULL check. 
pipeline cannot be NULL since pipeline->layout->num_sets was just
checked.

Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking pipeline suggests that it may be
null, but it has already been dereferenced on all paths leading to
the check.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7521>
 2020-11-09 18:02:21 -08:00
Vinson Lee f8844d5c72 swr: Initialize FetchJit member mpFetchInfo in constructor. 
Fix defect reported by Coverity Scan.

Uninitialized pointer field (UNINIT_CTOR)
uninit_member: Non-static class member mpFetchInfo is not
initialized in this constructor nor in any functions that it
calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7359>
 2020-11-09 17:02:50 -08:00
Dylan Baker a8467191c3 Reset new features for 21.0 development cycle 2020-11-09 16:21:18 -08:00
Dylan Baker a706bac098 Bump version for 21.0 devel 2020-11-09 16:20:45 -08:00
Anuj Phogat 3c4e43e72b intel: Pointer to SCISSOR_RECT array should be 64B aligned 
v2: Apply the workaround to all gen hardawre

Ref: GEN:BUG:1409725701
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7463>
 2020-11-09 21:29:04 +00:00
Arcady Goldmints-Orlov a1a365e818 broadcom/compiler: Allow spills of temporaries from TMU reads 
Since spills and fills use the TMU, special care has to be taken to
avoid putting one between a TMU setup instruction and the corresponding
reads or writes. This change adds logic to move fills up and move spills
down to avoid interrupting such sequences.

This allows compiling 6 more programs from shader-db. Other stats:

total spills in shared programs: 446 -> 446 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0

total fills in shared programs: 606 -> 610 (0.66%)
fills in affected programs: 38 -> 42 (10.53%)
helped: 0
HURT: 2

total instructions in shared programs: 19330 -> 19363 (0.17%)
instructions in affected programs: 3299 -> 3332 (1.00%)
helped: 0
HURT: 5

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6606>
 2020-11-09 20:45:58 +00:00
Samuel Pitoiset 1c5271346a nir/algebraic: optimize bitfield_select(a, b, 0) to iand(a, b) 
(src0 & src1) | (~src0 & src2) to (src0 & src1).

fossils-db (Polaris10):
Totals from 873 (0.63% of 138014) affected shaders:
SGPRs: 33781 -> 33733 (-0.14%)
VGPRs: 37704 -> 37520 (-0.49%); split: -0.51%, +0.02%
CodeSize: 3861460 -> 3853424 (-0.21%); split: -0.21%, +0.00%
MaxWaves: 5306 -> 5305 (-0.02%)
Instrs: 743798 -> 743486 (-0.04%); split: -0.04%, +0.00%
Cycles: 10962244 -> 10960936 (-0.01%); split: -0.01%, +0.00%
VMEM: 128309 -> 128350 (+0.03%); split: +0.33%, -0.30%
SMEM: 44797 -> 44113 (-1.53%); split: +0.02%, -1.54%
Copies: 71875 -> 71674 (-0.28%); split: -0.31%, +0.03%
PreSGPRs: 23484 -> 23479 (-0.02%)
PreVGPRs: 34582 -> 34529 (-0.15%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7479>
 2020-11-09 19:51:27 +00:00
Boris Brezillon d47969eb5e pan/bi: Add support for load_instance_id 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 5cd1d8c1ed pan/bi: Add support for load_vertex_id 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 255f7842c7 panfrost: Allow linear ZS resources on Bifrost 
Linear Z/S buffers should be handled correctly now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 4995a4c03a pan/bi: Add support for ushr 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon af70987b36 pan/bi: Add support for ishr 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 3257ad21f3 pan/bi: Fix ARSHIFT definitions 
src1 exists, and must be set to ZERO. If we don't add this source,
lane2 refers to src2 which does not exists.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 2a80b2d0cd pan/bi: Move bitwise op packing out of bi_pack_fma() 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon cc0950722c pan/bi: Get rid of bi_emit_ld_uniform() 
Now that we lower uniforms to UBO we can get rid of bi_emit_ld_uniform().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon fd265fa020 pan/bi: Lower uniforms to UBO 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 09da82cbdc pan/bi: Add support for load_ubo 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 87e2169cb9 pan/bi: Fix swizzle handling in bi_copy_src() 
The number of src swizzle to initialize depends on the number of source
properties (size and number of components) not the destination ones.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 2522f509a3 pan/bi: Support centroid and sample interpolations 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon ca5a00a70c pan/bi: Extract LD_VAR sample field from ins->load_vary.interp_mode 
So we can extend bi_emit_ld_vary() to support centroid and sample modes.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 1692088d05 panfrost: Expose GLES3 features on Bifrost when PAN_MESA_DEBUG=deqp 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
 2020-11-09 20:36:50 +01:00
Boris Brezillon 23dbf7964b panfrost: Force late pixel kill when depth/stencil is written from the FS 
If we don't do that, pixels might be killed early thus preventing the
fragment shader from being called and updating the depth/stencil value.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7501>
 2020-11-09 19:23:41 +00:00
SureshGuttula 956228da3a radeon/vcn : Corrected dpb_size calculation for VP9_2 
Currently dpb_size for VP9 profile0 and profile2 is same eventhough
for profile2 dpb_size is  multiplied by extra 3/2 and we are
seeing VM_L2_PROTECTION_FAULT error and ring vcn_dec timeout because
of less dpb_size for VP9_2.

This patch will correct dpb_size for VP9_2 and fixes the issue.

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7480>
 2020-11-09 19:14:22 +00:00
Jason Ekstrand 68092df8d8 intel/nir: Lower 8-bit ops to 16-bit in NIR on Gen11+ 
Intel hardware supports 8-bit arithmetic but it's tricky and annoying:

  - Byte operations don't actually execute with a byte type.  The
    execution type for byte operations is actually word.  (I don't know
    if this has implications for the HW implementation.  Probably?)

  - Destinations are required to be strided out to at least the
    execution type size.  This means that B-type operations always have
    a stride of at least 2.  This means wreaks havoc on the back-end in
    multiple ways.

  - Thanks to the strided destination, we don't actually save register
    space by storing things in bytes.  We could, in theory, interleave
    two byte values into a single 2B-strided register but that's both a
    pain for RA and would lead to piles of false dependencies pre-Gen12
    and on Gen12+, we'd need some significant improvements to the SWSB
    pass.

  - Also thanks to the strided destination, all byte writes are treated
    as partial writes by the back-end and we don't know how to copy-prop
    them.

  - On Gen11, they added a new hardware restriction that byte types
    aren't allowed in the 2nd and 3rd sources of instructions.  This
    means that we have to emit B->W conversions all over to resolve
    things.  If we emit said conversions in NIR, instead, there's a
    chance NIR can get rid of some of them for us.

We can get rid of a lot of this pain by just asking NIR to get rid of
8-bit arithmetic for us.  It may lead to a few more conversions in some
cases but having back-end copy-prop actually work is probably a bigger
bonus.  There is still a bit we have to handle in the back-end.  In
particular, basic MOVs and conversions because 8-bit load/store ops
still require 8-bit types.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7482>
 2020-11-09 18:58:51 +00:00
Jason Ekstrand b98f0d3d7c intel/nir: Lower 8-bit scan/reduce ops to 16-bit 
We can't really support these directly on any platform.  May as well let
NIR lower them.  The NIR lowering is potentially one more instruction
for scan/reduce ops thanks to not being able to do the B->W conversion
as part of SEL_EXEC.  For imax/imin exclusive scan, it's yet another
instruction thanks to the extra imax/imin NIR has to insert to deal with
the fact that the first live channel will contain the identity value
which, when signed, will cast wrong.  However, it does let us drop some
complexity from our back-end so it's probably worth it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7482>
 2020-11-09 18:58:51 +00:00
Jason Ekstrand 3ad2d85995 intel/nir: Refactor lower_bit_size_callback 
We want to use it for more than just ALU.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7482>
 2020-11-09 18:58:51 +00:00
Jason Ekstrand f95665cfeb nir/lower_bit_size: Add support for lowering subgroup ops 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7482>
 2020-11-09 18:58:51 +00:00
Jason Ekstrand 2c4b47184d nir/lower_bit_size: Pass a nir_instr to the callback 
This way we can start supporting more than just ALU ops.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7482>
 2020-11-09 18:58:51 +00:00
Jason Ekstrand 15c6e05a72 nir/lower_bit_size: Don't cast comparison results 
Some ALU ops (comparisons being the primary example) have a fixed
bit-size destination and, in that case, we don't want to insert a
conversion on the destination.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7482>
 2020-11-09 18:58:51 +00:00
Rhys Perry 86ef139bf4 radv: implement VK_EXT_shader_image_atomic_int64 
The extension is only exposed on ACO and LLVM 11+ because of a LLVM bug.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7234>
 2020-11-09 18:28:59 +00:00
Rhys Perry 9f43268772 ac/nir: implement 64-bit images 
64-bit image atomics only work with LLVM 11+ because of a LLVM bug.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7234>
 2020-11-09 18:28:59 +00:00
Rhys Perry 5b81e80fb6 aco: implement 64-bit images 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7234>
 2020-11-09 18:28:59 +00:00
Rhys Perry 8570de72f5 amd/common: add PIPE_FORMAT_R64_{UINT,SINT} to GFX10 format table 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7234>
 2020-11-09 18:28:59 +00:00
Rhys Perry cff195087f util: add mapping from Vulkan to Gallium R64 integer formats 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7234>
 2020-11-09 18:28:59 +00:00
Louis-Francis Ratté-Boulianne bcc3d53587 gallium: Fix NIR validation when lowering polygon stipple 
The fmul operation takes the maximum number of components from either
of its operands. We only need to use 2 components from the fragment
coordinates.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7507>
 2020-11-09 18:12:27 +00:00
Erik Faye-Lund 441feda0bb gallium/util: do not pass undefined sample-count 
We forgot to initialize the sample_count member here, leading to it
being undefined. This causes problems on MSVC when compiling in
debug-mode, where we get a run-time error for using an undefined
variable.

To avoid similar problems in the future if more fields are added,
let's initialize the whole struct to zero to start with. This also
allows us to remove a no-longer-needed zero-initialization.

Fixes: cf170616da ("gallium: Add a util_blitter path for using a custom VS and FS.")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7503>
 2020-11-09 17:51:56 +00:00
Samuel Pitoiset bae5487659 aco: optimize v_and(a, v_subbrev_co(0, 0, vcc)) -> v_cndmask(0, a, vcc) 
fossils-db (Vega10):
Totals from 7786 (5.70% of 136546) affected shaders:
SGPRs: 517778 -> 518626 (+0.16%); split: -0.01%, +0.17%
VGPRs: 488252 -> 488084 (-0.03%); split: -0.04%, +0.01%
CodeSize: 42282068 -> 42250152 (-0.08%); split: -0.16%, +0.09%
MaxWaves: 35697 -> 35716 (+0.05%); split: +0.06%, -0.01%
Instrs: 8319309 -> 8304792 (-0.17%); split: -0.18%, +0.00%
Cycles: 88619440 -> 88489636 (-0.15%); split: -0.16%, +0.01%
VMEM: 2788278 -> 2780431 (-0.28%); split: +0.06%, -0.35%
SMEM: 570364 -> 569370 (-0.17%); split: +0.12%, -0.30%
VClause: 144906 -> 144908 (+0.00%); split: -0.05%, +0.05%
SClause: 302143 -> 302055 (-0.03%); split: -0.04%, +0.01%
Copies: 579124 -> 578779 (-0.06%); split: -0.14%, +0.08%
PreSGPRs: 327695 -> 328845 (+0.35%); split: -0.00%, +0.35%
PreVGPRs: 434280 -> 433954 (-0.08%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7438>
 2020-11-09 17:36:42 +00:00
Jason Ekstrand 2bbe01b186 spirv: Add support for SPV_EXT_shader_image_atomic_int64 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7509>
 2020-11-09 17:17:40 +00:00
Jason Ekstrand 5a3e22018d nir: Allow 64-bit image atomics 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7509>
 2020-11-09 17:17:39 +00:00
Jason Ekstrand 79f477c3c6 compiler/types: Add 64-bit image types 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7509>
 2020-11-09 17:17:39 +00:00
Jason Ekstrand d44c76be85 util,gallium: Add new 64-bit integer formats 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7509>
 2020-11-09 17:17:39 +00:00
Jason Ekstrand b725fbd191 nir: Validate image atomic formats 
GLSL requires that image atomics have formats and there are rules about
things matching properly.  We should enforce those in NIR unless we have
reason to do otherwise.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7509>
 2020-11-09 17:17:39 +00:00
Jason Ekstrand 72f1c9aef5 nir: Print formats on image intrinsics as text 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7509>
 2020-11-09 17:17:39 +00:00
Jason Ekstrand d22fafa20b spirv: Update headers and metadata from latest Khronos commit 
This corresponds to 5ab5c96198f30804a6a29961b8905f292a8ae600
("Reserve additional loop control bit for Intel extension (NoFusionINTEL) (#175)") in
https://github.com/KhronosGroup/SPIRV-Headers.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7509>
 2020-11-09 17:17:39 +00:00
Erik Faye-Lund 2acdcf0b31 libgl-gdi: support building without softpipe 
While we do need *some* fallback-driver, there's no good reason to
*always* require that to be Softpipe. LLVMpipe for instance does the job
just fine.

This makes the minimal build a bit smaller on Windows.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7506>
 2020-11-09 16:58:45 +00:00
Alyssa Rosenzweig d7f7d890f1 panfrost: Add missing Collabora copyright notices 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7502>
 2020-11-09 16:45:25 +00:00
Alyssa Rosenzweig 14bbc24b60 pan/mdg: Add missing Collabora copyright notices 
On a few of the older files.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7502>
 2020-11-09 16:45:25 +00:00
Erik Faye-Lund 92374aebe2 spirv: correct sematic-typo 
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7504>
 2020-11-09 16:31:02 +00:00
Daniel Stone fc2814417e CI: Disable Panfrost T760 
For some unknown reason, both RK3288 Chromebooks went catatonic over the
weekend. Disable them until we can get them fixed.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7508>
 2020-11-09 15:11:33 +00:00