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Author SHA1 Message Date
Samuel Pitoiset ea0e22da44 zink: use warn_missing_feature for missing modifier support 
To avoid spamming VKCTS output.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25636>
 2023-10-10 11:44:12 +00:00
Erik Faye-Lund 2ac2268ce7 ci/etnaviv: allow failure on failing test 
This test has been failing every nightly pipeline on the CI for a long,
long time. It seems nobody is currently interested in fixing it, so
let's just allow the failure for now.

See https://gitlab.freedesktop.org/mesa/mesa/-/issues/9967

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25635>
 2023-10-10 11:28:52 +00:00
Erik Faye-Lund 7368a89752 ci/etnaviv: update ci expectation 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25635>
 2023-10-10 11:28:52 +00:00
Danylo Piliaiev 8fe599ed1c tu: Zero init tu_render_pass and tu_subpass for dynamic rendering 
The way we init render pass related structures is dangerous with when
structs are not zero initialized - too easy to miss a field. There
were already at least two issues with it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25592>
 2023-10-10 09:42:15 +00:00
Danylo Piliaiev 964a27aa39 tu: Fix stale tu_render_pass_attachment::store_stencil with dyn rendering 
Attachment initialization helpers expect zeroed memory by default.

Fixes a hang when running Subnautica with TU_DEBUG="gmem".
See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8702#note_1932003

Fixes: ed125e6cca
("tu: Initial support for dynamic rendering")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25592>
 2023-10-10 09:42:15 +00:00
Alyssa Rosenzweig 335cf5f22f nir: Use a tagged pointer for nir_src parents 
This allows us to pack the is_if boolean into the bottom bit of the parent
pointer, eliminating the boolean and hence shrinking the nir_src by 8 bytes (due
to the extra 63 bits of padding incurred in the old layout).

Because all access is forced through helpers now, this is a local change.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
 2023-10-10 04:58:05 -04:00
Alyssa Rosenzweig 316af8c965 nir: Assert the nir_src union is used safely 
It is undefined behaviour in C to read a different member of a union than was
written. Nothing in-tree should be using this behaviour with the nir_src union:
nir_if should never be read as nir_instr and vice versa. Assert this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
 2023-10-10 04:58:05 -04:00
Alyssa Rosenzweig c39896b17b nir: Use getters for nir_src::parent_* 
First, we need to give the parent_instr field a unique name to be able to
replace with a helper.  We have parent_instr fields for both nir_src and
nir_def, so let's rename nir_src::parent_instr in preparation for rework.

This was done with a combination of sed and manual fix-ups.

Then we use semantic patches plus manual fixups:

    @@
    expression s;
    @@

    -s->renamed_parent_instr
    +nir_src_parent_instr(s)

    @@
    expression s;
    @@

    -s.renamed_parent_instr
    +nir_src_parent_instr(&s)

    @@
    expression s;
    @@

    -s->parent_if
    +nir_src_parent_if(s)

    @@
    expression s;
    @@

    -s.renamed_parent_if
    +nir_src_parent_if(&s)

    @@
    expression s;
    @@

    -s->is_if
    +nir_src_is_if(s)

    @@
    expression s;
    @@

    -s.is_if
    +nir_src_is_if(&s)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
 2023-10-10 04:58:05 -04:00
Alyssa Rosenzweig ad619da3bc nir: Use set_parent_instr internally 
This properly clears is_if.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
 2023-10-10 04:58:04 -04:00
Alyssa Rosenzweig 19f8e0e3aa nir: Add trivial nir_src_* getters 
These will become nontrivial later in the series. For now these have no smarts
in them, in order to make the conversion completely mechanical.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
 2023-10-10 04:58:04 -04:00
Alyssa Rosenzweig 4753ce7d72 lima/pp: Do not use union undefined behaviour 
It is invalid to read parent_instr for an if-use (or parent_if for a
non-if-use). Make sure we read the right one when handling if-uses.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
 2023-10-10 04:58:04 -04:00
Samuel Pitoiset e1622dcca1 radv: fix IB alignment 
This re-introduces "radv: fix alignment of DGC command buffers" and
"radv/amdgpu: fix alignment of command buffers" which were valid
changes.

IBs need to be aligned to the IB size requirement, not the number of
padded NOPs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25588>
 2023-10-10 06:26:59 +00:00
Dave Airlie af062126ae lavapipe: expose planar ycbcr formats and new ycbcr features 
This enables some extensions and a bunch of formats for ycbcr
support.

dEQP-VK.api.info.format_properties.g8_b8_r8_3plane_420_unorm,Fail
dEQP-VK.api.info.format_properties.g8_b8r8_2plane_420_unorm,Fail

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie e6ae51014d lavapipe: handle planes in texture lowering. 
This uses the descriptor set info to lower the texture/sampler
handlers properly using the stride.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie a13a07d166 lavapipe: add descriptor sets bindings for planar images 
This adds strided descriptor bindings that are used to handle
planar image/samplers.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie cfdad158a1 lavapipe: handle planes in get image sub resource 
image sub resources need to take planes into account in the calculations.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie 64cf0d47b0 lavapipe: handle planes in copies 
This adds plane support to the various copy paths.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie d2671d3c17 lavapipe: allocate image and image view planes. 
This allocate planes and handles disjoint.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie a368e3f8d5 lavapipe: start introducing planes structure. 
this just introduces a single plane and refactors code to use it.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie 9bbb21eecd lavapipe: cleanup copy code to use a local region variable. 
This should make no functional difference, except cleanup the code.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:07 +00:00
Dave Airlie b52261cb9c lavapipe: convert sampler to use vk base class. 
This just makes things a bit cleaner, and reuses the common code.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:06 +00:00
Dave Airlie 66c118495e llvmpipe: don't support planar formats for buffers. 
This stops lavapipe exposing incorrect support.

Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:06 +00:00
Dave Airlie d1622204b5 lavapipe: don't emit blit src/dst for subsampled formats. 
Fixes dEQP-VK.api.info.format_properties.b8g8r8g8_422_unorm

Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:06 +00:00
Dave Airlie b66afc2a54 llvmpipe: don't create texture functions for planar textures. 
Since we can't sample from these directly, just don't create the
functions.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:06 +00:00
Dave Airlie f9e7997ac8 lavapipe: support host image copying on compressed texture formats 
dEQP-VK.image.host_image_copy.query.linear.bc5_snorm_block,Fail
dEQP-VK.image.host_image_copy.query.linear.bc7_unorm_block,Fail
dEQP-VK.image.host_image_copy.query.optimal.bc5_snorm_block,Fail
dEQP-VK.image.host_image_copy.query.optimal.bc7_unorm_block,Fail

Fixes: 9e9d90c6c3 ("lavapipe: VK_EXT_host_image_copy")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:06 +00:00
Dave Airlie 21a79acaa7 lavapipe: fix subresource layers asserts 
dEQP-VK.api.copy_and_blit.copy_commands2.blit_image.simple_tests.array.all_remaining_layers

Fixes: 35c02f79c9 ("lavapipe: add some asserts for blit region extents")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:06 +00:00
Dave Airlie 05047ceced lavapipe: fix some whitespace in advance of other changes. 
This is just some tab and trailing whitespace removal.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
 2023-10-10 04:37:06 +00:00
Qiang Yu 0e97568aed radeonsi: enable aco compile for part mode ps 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:41 +08:00
Qiang Yu 333d6f007a radeonsi: add ps epilog shader part build 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:36 +08:00
Qiang Yu 42907365f8 radeonsi: fill aco shader info for ps part 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:32 +08:00
Qiang Yu a994db1d8f radeonsi: extract si_get_ps_epilog_args to be shared with aco 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:28 +08:00
Qiang Yu e41833a6a2 radeonsi: add ps prolog shader part build 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:24 +08:00
Qiang Yu 5263a9e364 ac,radeonsi: remove unused ps prolog key fields 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:20 +08:00
Qiang Yu 1728111c29 radeonsi: extract si_get_ps_prolog_args to be shared with aco 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:16 +08:00
Qiang Yu 9594a579b2 radeonsi: extract si_prolog_get_internal_binding_slot 
To be shared with ps prolog.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:11 +08:00
Qiang Yu c4643477cd radeonsi: init spi_ps_input_addr for part mode ps 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:10:07 +08:00
Qiang Yu c77a57b981 radeonsi: reduce sgpr count for scratch_offset when aco 
aco add scratch_offset to shader args explicitly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
 2023-10-10 11:09:48 +08:00
Qiang Yu 5ef7c54829 aco: wait memory ops done before go to next shader part 
Next part don't know whether p_end_with_regs args are loaded from
memory ops or not, need to wait it's done here.

Other memory load needs to be waited too like:
  a = load_mem()
  b = ...
  if (...) {
    wait_mem(a)
    store_mem(a)
  }
  p_end_with_regs(b)

"a" still needs to be waited, otherwise next shader part regs may
be overwritten by unfinished memory loads.

Memory stores are waited too. When >=gfx10 and last VGT has no
parameter export, we need to wait all memeory stores done before
pos export (see ac_nir_export_position). So when merged shader
(ES+GS or VS+GS) is partially built, first stage needs to wait
all memory stores done, otherwise second stage don't know if
any memory stores pending before.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Signe-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu 5ba68f92b4 aco: create exit block for p_end_with_regs to branch to 
To handle ps discard in radeonsi part mode shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu bf25a7f59b aco: fix assertion fail when program contains empty block 
radeonsi may generate empty main shader or an empty exit block
for p_end_with_regs to jump to.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu 6eb0910d45 aco: do not fix_exports when program has epilog 
PS with epilog does not need to fix_exports. And radeonsi use
p_end_with_regs so does not have jump instruction at last.

radeonsi may also have exec restore instruction, so may break
before reach to p_end_with_regs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu f97a701d89 aco,radv,radeonsi: pass spi ps input ena and addr 
radeonsi may pass different ena and addr when part mode shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu c9c18d3da5 aco: compact ps expilog color export for radeonsi 
radeonsi need to compact color export for ps epilog while radv does not.
radv will fill empty color slot, so won't affected by this change.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu 1517aa7a8a aco,radv: add radeonsi spec ps epilog code 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu 9972a385fb aco: simplify export_fs_mrt_color 
It's now used by ps epilog only.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu 77d5966661 aco,radv: rename ps epilog info inputs to colors 
Will add other mrtz args for radeonsi.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu d8fa106c17 aco,radv: remove unused ps epilog info fields 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:34 +00:00
Qiang Yu 57b0f19582 aco: add create_fs_end_for_epilog for radeonsi 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:33 +00:00
Qiang Yu 90c901a987 aco: handle ps outputs from radeonsi 
radeonsi will keep outputs <FRAG_RESULT_DATA0.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:33 +00:00
Qiang Yu 49250f9fc5 aco: add ps prolog generation for radeonsi 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
 2023-10-10 02:36:33 +00:00