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18217 Commits

Author SHA1 Message Date
Georg Lehmann 4683187f49 radv/nir/lower_cmat: load gfx11 8bit ACC using the B layout to get aligned loads 
This allows us to use aligned loads that can be vectorized, without any
downside as 8bit scalar loads always write 16bits of a register.

Foz-DB Navi31:
Totals from 10 out of 14 FSR4 shader:
MaxWaves: 71 -> 68 (-4.23%)
Instrs: 60146 -> 59781 (-0.61%); split: -0.67%, +0.06%
CodeSize: 412448 -> 413428 (+0.24%); split: -0.11%, +0.35%
VGPRs: 2112 -> 2160 (+2.27%)
SpillVGPRs: 89 -> 68 (-23.60%)
Scratch: 11776 -> 8704 (-26.09%)
Latency: 196628 -> 193770 (-1.45%); split: -2.62%, +1.17%
InvThroughput: 224944 -> 226274 (+0.59%); split: -0.02%, +0.61%
VClause: 862 -> 796 (-7.66%)
Copies: 3166 -> 3342 (+5.56%); split: -6.22%, +11.78%
Branches: 37 -> 38 (+2.70%)
PreSGPRs: 311 -> 312 (+0.32%)
PreVGPRs: 2153 -> 2214 (+2.83%); split: -1.35%, +4.18%
VALU: 51073 -> 51448 (+0.73%); split: -0.03%, +0.77%
SALU: 1072 -> 1074 (+0.19%)
VMEM: 3275 -> 2765 (-15.57%)
VOPD: 1739 -> 1783 (+2.53%); split: +7.99%, -5.46%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36117>
 2025-07-30 07:25:51 +00:00
Marek Olšák 8d3e76c250 nir: split nir_move_load_frag_coord from nir_move_load_input 
It's a pure system value on AMD, not an input.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36357>
 2025-07-29 16:20:48 -04:00
Antonio Ospite 0dd8051f34 radv: fix returning _Bool instead of pointer 
When building for C23 the compiler warns about returning a boolean when
a different type is expected instead.

Change the code to return NULL instead of false, fixing the following
errors:

-----------------------------------------------------------------------
../src/amd/vulkan/radv_pipeline_cache.c: In function ‘radv_pipeline_cache_object_search’:
../src/amd/vulkan/radv_pipeline_cache.c:338:14: error: incompatible types when returning type ‘_Bool’ but ‘struct radv_pipeline_cache_object *’ was expected
  338 |       return false;
      |              ^~~~~
../src/amd/vulkan/radv_pipeline_cache.c:352:14: error: incompatible types when returning type ‘_Bool’ but ‘struct radv_pipeline_cache_object *’ was expected
  352 |       return false;
      |              ^~~~~
-----------------------------------------------------------------------

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36323>
 2025-07-29 14:07:06 +00:00
llyyr c869971d05 radv: don't set HOST_IMAGE_TRANSFER_BIT if host_image_copy not enabled 
This can't work if the extension isn't enabled, so only set if the
extension is enabled.

Fixes: d89b11011f ("radv: add support for formats with host-transfer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36400>
 2025-07-29 13:48:59 +00:00
Nagulendran, Iswara 6088dbe05c amd/vpelib: Fix cost profiling support 
Add additional changes/logs to profile total register writes.

Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:25 +00:00
Chang, Tomson 02beb30d6b amd/vpelib: Update register header and definitions macros 
Update header and related macros and functions

Reviewed-by: Min-Hsuan You <Min-Hsuan.You@amd.com>
Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:25 +00:00
Chan, Roy 08fd9aab30 amd/vpelib: fix memory corruption 
[WHY]
Wrong structure size being allocated

[HOW]
fixed the structure size during allocation

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:25 +00:00
Nagulendran, Iswara 74c88f740f amd/vpelib: Fix Issues with Background Color insertions 
[WHY]
Background Color Insertion, test cases involving studio output fails

[HOW]
Move background color convertion into revision specific resource
files and isolated what needed to be executed for VPE

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:25 +00:00
Assadian, Navid b529d38ae9 amd/vpelib: Exit when VPE not support in debug 
When the debug flag is set to assert when vpe is not supported, instead
of assert it is preferable to exit so the CI aborts the process instead
of waiting on the assert message.

[WHY]
In debug mode for CI, when assert the process doesn't abort and the CI
terminates on time out.

[HOW]
Using exit instead of assert

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Kovac, Krunoslav 5b8b5c4c49 amd/vpelib: Fix Possible dereferencing null 
pointer issue

[WHY]
Mostly dereferencing possible null ptrs

[HOW]
Add checks / refactor code.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Chang, Tomson 48495c142a amd/vpelib: Add missing swizzle and dcc info 
Add missing swizzle mode and dcc info

Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Reviewed-by: Jude Shih <Jude.Shih@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Hsieh, Mike d281a5587d amd/vpelib: add max/min input output capability 
[WHY]
Capability need to show max and min input/output size.

[HOW]
Add max_input_size, max_ouptut_size, min_output_size and min_imput_size.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Hsieh, Mike 6b279abcac amd/vpelib: bug fix: remove unnecessary free 
[WHY]
vpe_priv.resource should not be freed when destroy resource

[HOW]
Remove unnecessary free.

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Brendan Steve Leder <BrendanSteven.Leder@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Hsieh, Mike e1ff093e63 amd/vpelib: add format, colorspace check function 
[WHY]
VPE does not support pixel format and colorspace support check.

[HOW]
add vpe_create_engine function to support stateless API.
Add new function to support pixel format check and colorspace support
check.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Agate, Jesse 0541d73cbd amd/vpelib: Use Ceil Division Macro 
Use available ceil division macro

[WHY]
Code Cleanup

[HOW]
Use available macro

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Georg Lehmann b12db991eb aco/gfx10: optimize subgroupRotate(x, 32) and subgroupShuffleXor(x, 32) 
We don't have v_permlane64_b32 yet, but we can still optimize it using
shared vgprs. Using the DPP16 row mask, we can even avoid writing exec.

With v0 input/output and v24/v25 as shared vgprs, this results in:
v_mov_b32_dpp v24, v0 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0xf
v_mov_b32_dpp v25, v0 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
v_mov_b32_dpp v0, v24 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
v_mov_b32_dpp v0, v25 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0xf

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36390>
 2025-07-29 06:33:20 +00:00
Georg Lehmann eb4df58a3d aco/isel: refactor shared vgpr usage 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36390>
 2025-07-29 06:33:20 +00:00
Georg Lehmann 8a2aca8d6f aco/select_alu: avoid vector get_alu_src for instructions with scalar operands 
Foz-DB Navi21:
Totals from 1 (0.00% of 80237) affected shaders:
Instrs: 22 -> 21 (-4.55%)
CodeSize: 112 -> 108 (-3.57%)
Latency: 392 -> 386 (-1.53%)
InvThroughput: 25 -> 24 (-4.00%)
Copies: 4 -> 3 (-25.00%)
PreVGPRs: 8 -> 4 (-50.00%)
VALU: 10 -> 9 (-10.00%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35728>
 2025-07-29 06:07:15 +00:00
Georg Lehmann ad9c340d86 aco: insert VALU s_delay_alu for WMMA 
This should avoid some SIMD stalls.

I think this special case was added to try to handle this case:

First Instruction: WMMA
Second Instruction: WMMA instruction with same VGPR of previous WMMA instruction’s Matrix D as Matrix C
Stall if the first and second instruction are not the same type of WMMA or use ABS/NEG on SRC2 of the second instruction

If I read it correctly, we shouldn't need a delay if the type is the same and no
modifier is used. That's kind of complex to handle, so leave it for now.
Not inserting any delays likely hurts more than this.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36328>
 2025-07-29 05:48:29 +00:00
Georg Lehmann 413d0d2ec8 aco/statistics: update GFX12 WMMA cost 
Based on marketing numbers, but they seem to match RGP.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36328>
 2025-07-29 05:48:29 +00:00
Georg Lehmann 8f61c85880 aco/statistics: add latency to WMMA 
Assume the normal VALU latency of 4 cycles.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36328>
 2025-07-29 05:48:29 +00:00
Georg Lehmann 004f8aa2f4 aco: optimize get_alu_src with constant source and size > 1 
Emulated FSR4, Navi31:
Totals from 14 (100.00% of 14) affected shaders:
MaxWaves: 130 -> 131 (+0.77%)
Instrs: 67887 -> 67470 (-0.61%); split: -0.70%, +0.09%
CodeSize: 464428 -> 461668 (-0.59%); split: -0.67%, +0.07%
VGPRs: 2544 -> 2520 (-0.94%)
SpillVGPRs: 92 -> 89 (-3.26%)
Latency: 256823 -> 257574 (+0.29%); split: -0.37%, +0.66%
InvThroughput: 253895 -> 252929 (-0.38%); split: -0.40%, +0.02%
VClause: 997 -> 984 (-1.30%); split: -2.11%, +0.80%
Copies: 4501 -> 3788 (-15.84%); split: -17.35%, +1.51%
PreSGPRs: 504 -> 519 (+2.98%)
PreVGPRs: 2460 -> 2448 (-0.49%)
VALU: 57202 -> 56726 (-0.83%); split: -0.88%, +0.05%
SALU: 1231 -> 1384 (+12.43%)
VMEM: 3807 -> 3801 (-0.16%)
VOPD: 2693 -> 2303 (-14.48%); split: +1.19%, -15.67%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36090>
 2025-07-25 11:33:00 +00:00
David Rosca cc7178b9eb radv/video: Use the new defines for H264 SPS info flags 
Also set gaps_in_frame_num_value_allowed_flag.

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36225>
 2025-07-25 09:32:08 +00:00
Konstantin Seurer 48d15c3cf8 radv/bvh: Specialize the update shader for geometryCount==1 
The geometry data can be loaded from push constants in that case.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35445>
 2025-07-25 09:05:13 +00:00
Konstantin Seurer b20ab07e4a radv/bvh: Update leaf nodes before refitting 
This should reduce latency between refitting nodes and their parent
nodes.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35445>
 2025-07-25 09:05:13 +00:00
Konstantin Seurer 33a694fe9b radv: Initialize base IDs when doing a BVH update with src!=dst 
Fixes: 2d48b2c ("radv: Use subgroup OPs for BVH updates on GFX12")
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35445>
 2025-07-25 09:05:12 +00:00
Konstantin Seurer 4a4251dc16 radv/bvh: Use a fixed indices midpoint on GFX12 
This saves a couple of loads inside the update shader.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35445>
 2025-07-25 09:05:12 +00:00
Konstantin Seurer 7ad02416f6 radv/bvh: Fix flush in bit_writer_skip_to 
If temp is not cleared, the next flushed dword will contain data from
the previous one.

Fixes: 97f6287 ("radv: Use the BVH8 format on GFX12")
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35445>
 2025-07-25 09:05:11 +00:00
Konstantin Seurer 6201e24307 radv: Only write leaf node offsets when required 
They are only used for serialization and position fetch which makes them
unnecessary most of the times.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35445>
 2025-07-25 09:05:11 +00:00
Konstantin Seurer 703a154f29 radv: Add and use RADV_OFFSET_UNUSED 
This deduplicates the logic to figure out what needs to be written.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35445>
 2025-07-25 09:05:10 +00:00
David Rosca 1dda9d56cb radv/video: Disable rate control modes for H265 encode on VCN1 
VCN1 doesn't have FW interface to enable cu_qp_delta with rate control
disabled, which means we can only support either rate control enabled or
disabled. Spec requires VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DISABLED_BIT_KHR
to always be supported, thus the rate control modes needs to be disabled
on VCN1.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:14 +00:00
David Rosca 627fdb368d radv/video: Fix session_init and rc_per_pic on VCN2 
Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:14 +00:00
David Rosca c11508ad41 radv/video: Fix setting H265 encode cu_qp_delta on VCN2 
Fixes H265 encoding with rate control disabled.

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:13 +00:00
David Rosca 70473690f5 radv/video: Fix encode bitstream buffer offset and alignment 
Caused issues on VCN2.

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:13 +00:00
David Rosca a30f91b71a radv/video: Add more encode session params overrides 
Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:13 +00:00
David Rosca e3715df4ee radv/video: Send slice control, spec misc and deblocking params every frame 
These params can change per frame, so we need to send the values
to firmware on every frame instead of only once at session init.

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:12 +00:00
David Rosca 947e647df8 radv/video: Always send the latency command 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:12 +00:00
David Rosca 8368e3519e radv/video: Set H264 encode cabac_init_idc and Cb/Cr QP offsets 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:11 +00:00
David Rosca df42301531 radv/video: Remove disabled slice header code for field encoding 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36353>
 2025-07-25 08:46:11 +00:00
David Rosca cefd4cfd83 radv/ci: Update navi10 and vega10 expected failures 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:41 +00:00
David Rosca 75c01206dc radv: Reject linear modifier for video decode DPB 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:41 +00:00
David Rosca b242c27c15 radv/video: Remove 10 to 8bit dithering support 
Only one format is supported now, so this is not needed.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:41 +00:00
David Rosca 4659be2c8b radv/video: Rework GetPhysicalDeviceVideoFormatPropertiesKHR 
Check if the profile is supported. Only return one format that
is supported by all requested profiles. Return error if the
requested profiles can't share the same format.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:41 +00:00
David Rosca 52fa173557 radv/video: Add radv_video_is_profile_supported 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:40 +00:00
David Rosca 8f6ceed8f5 radv/video: Set encodeInputPictureGranularity for AV1 encode 
Fixes: 37e71a5cb2 ("radv/video: add support for AV1 encoding")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:40 +00:00
David Rosca fd0c70aded radv/video: Add bit depth and profile check for VP9 decode 
Fixes: b8ac2d47e7 ("radv/video: add KHR_video_decode_vp9 support.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:40 +00:00
David Rosca bdad9e7e48 radv/video: Add bit depth and profile check for AV1 encode 
Fixes: 37e71a5cb2 ("radv/video: add support for AV1 encoding")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36311>
 2025-07-25 07:28:39 +00:00
Marek Olšák 09e607c385 nir: add access to load_smem_amd (for ACCESS_CAN_SPECULATE) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36099>
 2025-07-24 18:41:38 +00:00
Marek Olšák 688a639117 nir: add nir_tex_instr::can_speculate 
Set to true everywhere except:
- spirv_to_nir used by Vulkan
- bindless handles in GLSL
- some internal shaders and driver-specific code

Acked-by: Job Noorman <job@noorman.info>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36099>
 2025-07-24 18:41:38 +00:00
Valentine Burley 5d55b7e50c radeonsi/ci: Remove Fluster flakes, document failures 
Tighten the expectations.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36316>
 2025-07-24 15:04:38 +00:00