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Author SHA1 Message Date
Timur Kristóf e60fbb4dc9 ac/nir/ngg: Copy comment about LDS layout for NGG GS. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17706>
 2022-07-22 08:17:39 +00:00
Timur Kristóf b5abf4fb3d ac/llvm: Use gs_prim_id for NGG VS. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17706>
 2022-07-22 08:17:39 +00:00
Timur Kristóf 1e2663b62c ac/llvm: Add LLVM bug workaround to ac_build_mbcnt_add. 
LLVM always believes that this instruction's upper bound is the wave
size, regardless of ac_set_range_metadata and regardless of whether
the add source is used.

As a workaround, emit an extra add instruction.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17706>
 2022-07-22 08:17:39 +00:00
Timur Kristóf c9f8be9d58 ac/llvm: Implement load_num_subgroups for NGG shaders. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17706>
 2022-07-22 08:17:39 +00:00
Konstantin Seurer 1a95d43e55 radv: Simplify the meta init fail path 
Move most of the the cleanup into radv_device_init_meta.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17652>
 2022-07-22 07:51:14 +00:00
Konstantin Seurer b06e5535c0 radv: Use RADV_META_SUSPEND_PREDICATING 
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17625>
 2022-07-22 07:25:09 +00:00
Konstantin Seurer fdeca2ca0b radv: Add meta saving/restoring for predicating 
There are a bunch of places, where this is done manually.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17625>
 2022-07-22 07:25:09 +00:00
Dave Airlie 21dd305694 llvmpipe: fix aniso cube map arrays. 
There was a coordinate missing when you have cube map arrays,
and aniso sampling.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Fixes: ce2b711c0a ("gallivm: add support for anisotropic sampling.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17704>
 2022-07-22 14:18:39 +10:00
Yiwei Zhang 02d6d43f54 Revert "venus: suballocate more for layering" 
This reverts commit f96e25ae05.

It's causing vkbench oom failure on radv.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17701>
 2022-07-22 03:09:12 +00:00
Jason Ekstrand 2b4e34d9b0 zink: Mark depth/stencil visual tests as flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand a5952c362e vulkan: Don't assert VkGraphicsPipelineLibraryCreateInfoEXT::Flags == 0 
There are VUs that imply that this is a requirement but the CTS seems to
ignore it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand 0415d66c97 vulkan: Input assembly and depth/stencil can also be fully dynamic 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand ceccbc01f5 vulkan: Fix pipeline libraries with dynamic-only VI or FSR state 
When we initialize the graphics pipeline state, we skip VI and FSR state
if they're 100% dynamic.  We need to do this if the current set of
dynamic things contains VI/FSR or if the set of dynamic state already in
the vk_graphics_pipeline_state has them dynamic.  Look state->dynamic
after we've merged instead of just looking at the dynamic set from the
VkGraphicsPipelineCreateInfo we were passed.

Also, when we validate, we need to assume that VI and FSR exist or else
we'll assert if dynamic VI or FSR are set.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand e5e828e91d vulkan: Add a fully_dynamic_state_groups() helper 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand 00269c09d6 vulkan: Depth/stencil isn't fragment output state but multisample is 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand cc84d4ca66 vulkan: Multisample state isn't always included in fragment shader state 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand 50411bd786 vulkan: Record shader stages in vk_graphics_pipeline_state 
Some of our asserts and other checks depend on the total set of stages,
not just the stages set in the current pCreateInfo.  Recording the stage
mask lets us combine them in vk_graphics_pipeline_state_merge().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Jason Ekstrand eb1f00aaac vulkan: Allow up to 12 pointers in multialloc 
vk_graphics_pipeline_state_init() may allocate up to 12 things so expand
vk_multialloc accordingly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17696>
 2022-07-22 02:36:17 +00:00
Chia-I Wu 8ec81a4b11 turnip: fix an assertion with drm-shim 
Fixes

  deqp-vk: ../src/vulkan/runtime/vk_device.c:49:
  get_timeline_mode: Assertion `timeline_type == NULL' failed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17571>
 2022-07-22 02:11:14 +00:00
Chia-I Wu 2d2912f18a freedreno/drm-shim: add a660 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17571>
 2022-07-22 02:11:14 +00:00
Emma Anholt 7f4df969c9 Revert "ci/freedreno: Switch a630 to manual/disabled for lab maintenance." 
This reverts commit 7e381ba9fc.  2 new
boards are in place, bringing us from 7 to 9.  We hoped for 12, but have
ongoing power stability issues.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17662>
 2022-07-22 00:57:23 +00:00
Emma Anholt 94b4c0bc39 ci/turnip: Add a couple of missing a630 fails. 
Same as a618.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17662>
 2022-07-22 00:57:23 +00:00
Emma Anholt 8a7c4f4202 ci/turnip: Bump up the a630 full run timeout. 
Test runtime has crept up with more CTS tests and more features.  The last
vk_full 1/2 run I tried timed out at:

Pass: 268488, Fail: 2, ExpectedFail: 7, Warn: 1, Skip: 602571, Duration: 1:29:29, Remaining: 45

Rude.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17662>
 2022-07-22 00:57:23 +00:00
Emma Anholt d8fb219b2f ci/freedreno: Add some more known flakes for a630 from our IRC logs. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17662>
 2022-07-22 00:57:23 +00:00
Jesse Natalie fccd6e275c d3d12: Support clip halfz 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17567>
 2022-07-22 00:00:54 +00:00
Sil Vilerino 948c03bf58 d3d12: Enable VPP rotation, flip, alpha blend, crop, scaling via pipe_video_codec::process_frame 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:31 +00:00
Sil Vilerino 323cf5a68d d3d12: Add pipe_video_codec::process_frame implementation 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:31 +00:00
Sil Vilerino 345fd92092 va: Add support for VPP rotation, flip, alpha blend, crop, scaling 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:30 +00:00
Sil Vilerino d09cf4333c gallium/video: Add video post processing interface 
Add process_frame to pipe_video codec
Add new structures/caps for video post-processing with rotation,
flip, alpha blending, crop, and scaling, via the video engine.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:30 +00:00
Sil Vilerino 721d9eea81 va: Replace usage of entrypoint UNKNOWN with PROCESSING for VP 
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:30 +00:00
Sil Vilerino 74c5d01169 vl: Replace usage of entrypoint UNKNOWN with PROCESSING for VP 
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:30 +00:00
Sil Vilerino f5ab2ffd4e pipe/video: Add PIPE_VIDEO_ENTRYPOINT_PROCESSING 
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:30 +00:00
Sil Vilerino 6bf8798ecb d3d12: Video - Remove unused spCopyQueues from enc/dec objects 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17557>
 2022-07-21 22:40:30 +00:00
Lionel Landwerlin 1aa4a91dbf anv: allocate RT scratch in local memory 
Like a 100x (not joking) improvement.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17674>
 2022-07-21 22:19:41 +00:00
Timur Kristóf dd781c1ccb ac/nir/ngg: Create output variable for primitive ID export. 
This makes the RADV/LLVM backend happy and mitigates a crash.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17581>
 2022-07-21 21:53:29 +00:00
Timur Kristóf 22796d91ea aco: Remove hack for primitive ID export. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17581>
 2022-07-21 21:53:29 +00:00
Timur Kristóf b0a7db1d3b ac/nir/ngg: Move primitive ID workgroup barrier to proper place. 
Previously, it was in a divergent branch, therefore
it could hang the GPU when a workgroup had a primitive-only wave.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17581>
 2022-07-21 21:53:29 +00:00
Qiang Yu 754e43369d ac/nir/ngg: Decouple primitive ID store and primitive export. 
There's no dependency between them.

This can simplify the compiler backend translation by
always storing prim id before vertex export, which also
benefits the LLVM backend in latter changes.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17581>
 2022-07-21 21:53:29 +00:00
Jason Ekstrand 9965863a13 lavapipe: Use more Vulkan NIR heleprs 
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17644>
 2022-07-21 21:18:48 +00:00
Jason Ekstrand 8e99a7f5e3 vulkan: Call gather_xfb_info in vk_spirv_to_nir 
In particular, we now call it before running dead variables so we get
the XFB info even for things which are never written.  This fixes a 102
Vulkan CTS tests on ANV and probably turnip as well.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17644>
 2022-07-21 21:18:48 +00:00
Jason Ekstrand bd93d6f693 vulkan/nir: Don't remove dead XFB outputs 
Fixes: 21b405fbbc ("vulkan: Add a vk_shader_module_to_nir() helper")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17644>
 2022-07-21 21:18:48 +00:00
Jason Ekstrand 87ab287436 vulkan: Call lower_clip_cull_distance_arrays in vk_spirv_to_nir 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17644>
 2022-07-21 21:18:48 +00:00
Jordan Justen 85099804bf iris/bufmgr: Add assert and TODO comment for future small BAR uapi 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen d9ce788641 anv/allocator: Add assert and TODO comment for future small BAR uapi 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen 7cf67e9da3 iris: Set clear_color_unknown if the bo is not mappable 
Rework:
 * Ken: Check bo for IRIS_MMAP_NONE rather than the global
   intel_vram_all_mappable

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen 180aa4f3b2 iris/bufmgr: Set mmap_mode to IRIS_MMAP_NONE for lmem in small-BAR mode 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen 49b1b8b853 iris/bufmgr: Add all_vram_mappable which is currently always true 
This can be false on systems where the PCI Base Address Register (BAR)
is too small for the amount of VRAM. Eventually the kernel will be
able to tell us that a system can't map all of VRAM, and
`all_vram_mappable` will then be false.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen 618c871a23 iris/resource: Avoid mapping when not needed in iris_resource_init_aux_buf() 
We might not be able to map all vram buffers in the future, so only
map the buffer when actually required.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen b79da470f2 iris/resource: Assert that DG2 CCS buffers don't also try to set BO_ALLOC_SMEM 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen 7bd3a6b757 intel/dev: Add intel_vram_all_mappable() 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00