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2905 Commits

Author SHA1 Message Date
Francisco Jerez e4aca2ebaa intel/fs: Add separate constructor of fs_visitor for fragment shaders. 
To allow specifying the number of polygons that will be processed per
SIMD thread.

Rework:
 * Jordan: Add needs_register_pressure following
   09cdb77a92 ("intel/fs: report max register pressure in shader stats")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
 2023-12-22 18:05:30 +00:00
Francisco Jerez 1eff2fcb62 intel/compiler: Add polygon count statistic to brw_compile_stats. 
And use it in ANV in order to return a "SIMDNxM" name from
vkGetPipelineExecutablePropertiesKHR.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
 2023-12-22 18:05:30 +00:00
Francisco Jerez ccf9174655 intel/compiler: Add multipolygon dispatch fields to brw_wm_prog_data. 
Add fields that track the number of polygons processed per PS SIMD
thread (note that this might be lower than the value that was
specified to the compiler via brw_compile_fs_params if compilation at
the desired polygon count wasn't possible), and the dispatch width of
the multi-polygon PS kernel.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
 2023-12-22 18:05:30 +00:00
Francisco Jerez e7b1993376 intel/compiler: Add max_polygons FS compilation parameter. 
Add a brw_compile_fs_params parameter that specifies to the compiler
the maximum number of polygons that may be processed in parallel per
PS SIMD thread.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
 2023-12-22 18:05:30 +00:00
Caio Oliveira 55cde229d5 intel/compiler: Use glsl_type C helpers 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26707>
 2023-12-22 06:44:23 -08:00
Matt Turner f2c97440f2 intel: Only validate inst compaction if debugging a shader stage 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26791>
 2023-12-22 03:16:32 +00:00
Sviatoslav Peleshko 8f8cde4c60 intel/fs: Don't optimize DW*1 MUL if it stores value to the accumulator 
Fixes: a8b86459 ("i965/fs: Optimize a * 1.0 -> a.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9570
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25710>
 2023-12-19 13:32:23 +00:00
Kenneth Graunke 49b8ccbcdc intel/fs: Drop opt_register_renaming() 
In the past, multiple writes to a single register were pretty common,
but since we've transitioned to NIR, and leave the IR in SSA form for
everything not captured in a phi-web, the pattern of generating new
temporary registers at each step is a lot more common.

This pass isn't nearly as useful now.  Across fossil-db on Alchemist,
this affects only 0.55% of shaders, which fall into two cases:

- Coarse pixel shading pixel-X/Y setup.  There are a few cases where
  we write a partial calculation into a register, then have a second
  instruction read that as a source and overwrite it as a destination.
  While we could use a temporary here, it doesn't actually help with
  register pressure at all, since there's the same amount of values
  live at both instructions regardless.  So while this pass kicks in,
  it doesn't do anything useful.

- Geometry shader control data bits (5 shaders total).  We track masks
  for handling EndPrimitive in a single register across the program,
  and apparently in some cases can split the live range.  However, it's
  a single register...only in geometry shaders...which use EndPrimitive.
  None of them appear to be in danger of spilling, either.  So this tiny
  benefit doesn't seem to justify the cost of running the pass.

So, just throw it out.  It's not worth keeping.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26343>
 2023-12-19 11:07:18 +00:00
Kenneth Graunke 866205d4d7 intel/fs: Allow omitting the destination of A64 untyped atomics 
This works exactly the same as the other atomics and the missing
destination is already handled in lower_logical_sends().

Only affects 2 shaders in fossil-db (in Cyberpunk 2077), but the
cycle count drops by 4.23%.  Nice to have in place at any rate.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26343>
 2023-12-19 11:07:18 +00:00
Jordan Justen f170995e66 anv, blorp, iris: Update 3DSTATE_PS programming for xe2 
Rework:
 * Jordan: Move code into intel_update_ps_state()

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Dave Airlie f76f4be301 intel/compiler: move gen5 final pass to actually be final pass 
This got broken by the register conversion, this pass needs to be
after all the others.

Fixes: ce75c3c3fe ("intel: Switch to intrinsic-based registers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>
 2023-12-18 07:24:37 +00:00
Caio Oliveira bfc953add7 intel/compiler: Use C helpers to access builtin types 
Remove usage of C++ static members as they are going to be removed.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26658>
 2023-12-15 03:09:19 +00:00
Sagar Ghuge a4947f7bd8 intel/fs: Adjust destination size for load ubo on Xe2+ 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Sagar Ghuge e0ce94318b intel/fs: Adjust destination size for global load constant on Xe2+ 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Sagar Ghuge 11fea46bdc intel/fs: Adjust destination size for image size intrinsic 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Sagar Ghuge c426553658 intel/compiler: Adjust assertion in lower_get_buffer_size() for Xe2 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Caio Oliveira a8b2426419 intel/compiler: Use reference instead of pointer for fs_visitor 
Per Ian suggestion.  Also clear up a few unnecessary casts around the code and
use `s` for fs_visitor ("shader").  Note to include a reference in ntf we need
to set it during initialization, so create an explicit mem_ctx for it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira 77ab74ccc2 intel/compiler: Use reference instead of pointer for nir_to_brw_state 
Per Ian suggestion.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira 4e5fcccd01 intel/compiler: Create and use nir_to_brw() function 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira 38a42e5aa1 intel/compiler: Add ctor to fs_builder that just takes the shader 
Uses the dispatch_width from the shader (fs_visitor).  This was not
possible before because the dispatch_width was not part of
backend_shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira cf730adc58 intel/compiler: Make fs_builder include fs_visitor and not the other way 
This will allow fs_builder have a reference to an fs_visitor (a
"fs_shader" really), instead of a reference to a backend_shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira f5032c4d52 intel/compiler: Make fs_visitor not depend on fs_builder 
At this point this is more a header dependency due to inline functions,
so shuffle them around.  The end goal is to allow fs_builder have a
reference to a fs_visitor (really a fs_shader).

Note the header is still included, a later patch will move the includes
to the call-sites.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira 4f991dec00 intel/compiler: Remove fs_visitor::bld 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira 5b8ec015f2 intel/compiler: Don't use fs_visitor::bld in remaining places 
The remaining users can simply create a new builder at_end() if needed.
In many places a new builder object is already being constructed, so
just give more specific instructions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:14 +00:00
Caio Oliveira c73c1aa496 intel/compiler: Annotate and use nir_to_brw_state::bld 
Use the "current bld" in nir_to_brw_state more widely, and also replace it
with an annotated version when applicable (to associate it with a NIR
instruction being lowered).  After filling a block we reset it back to
the original value.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 34c28680b1 intel/compiler: Stop using fs_visitor::bld field in NIR conversion 
Provide its own builder in nir_to_brw_state.  Will allow eventually remove
the one in fs_visitor.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 79735fa783 intel/compiler: Move remaining NIR conversion fields to nir_to_brw_state 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 5cb189636d intel/compiler: Move nir_ssa_value into a local structure 
Create a nir_to_brw_state struct that is valid only during the
NIR to backend translation and use it for nir_ssa_values array.

This removes some NIR specific handling out of the fs_visitor -- nowadays
effectively an fs_shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira afe75d65be intel/compiler: Make NIR resources helpers static 
Remove get_nir_src_block() since it is not used anywhere.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira a7a27ee95e intel/compiler: Make NIR atomic conversion functions static 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 5777943381 intel/compiler: Make non-intrinsic NIR conversion functions static 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 2385d6087a intel/compiler: Make setup functions of NIR emission static 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 3899e6b1d8 intel/compiler: Make functions for NIR control flow conversion static 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 860ec33f9a intel/compiler: Make more functions in NIR conversion static 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira acca9dbf6b intel/compiler: Make a NIR intrinsic emission functions static 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira c12460b01e intel/compiler: Move NIR emission code to brw_fs_nir.cpp 
This is a preparation to reorganize NIR emission code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Caio Oliveira 1ef6415d22 intel/compiler: Remove unused headers 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26323>
 2023-12-12 19:36:13 +00:00
Ian Romanick 87cdcbd7d7 intel/compiler: Verify that DO is alone in the block 
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26439>
 2023-12-08 20:21:28 +00:00
Ian Romanick 65237f8bbc intel/fs: Don't add MOV instructions to DO blocks in combine constants 
There was a subtle bug related to CFG tracking. Namely, some branch
instructions may point *only* to the block after the DO instruction
for the loop. If the MOV instructions are in the DO block, the may not
have liveness properly tracked.

Like in !25132, having the MOV instructions in blocks that might
contain other instructions helps scheduling.

shader-db:

All Broadwell and newer Intel GPUs had similar results (Ice Lake shown)
total cycles in shared programs: 848577248 -> 848557268 (<.01%)
cycles in affected programs: 78256396 -> 78236416 (-0.03%)
helped: 361 / HURT: 18

fossil-db:

All Skylake and newer Intel GPUs had similar results (Ice Lake shown)
Totals:
Cycles: 15021501924 -> 15021372904 (-0.00%); split: -0.00%, +0.00%

Totals from 735 (0.11% of 656080) affected shaders:
Cycles: 676429502 -> 676300482 (-0.02%); split: -0.02%, +0.00%

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26439>
 2023-12-08 20:21:28 +00:00
Rohan Garg db6aaa691d intel/compiler: infer the number of operands using lsc_op_num_data_values 
nir_emit_global_atomic should utilize lsc_op_num_data_values to
infer the number of operands for global atomic ops, following the same
pattern as nir_emit_surface_atomic

Fixes: 90a2137 ('intel/compiler: Use LSC opcode enum rather than legacy BRW_AOPs')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26432>
 2023-12-07 14:40:24 +00:00
Rohan Garg 46d98a71ef intel/compiler: use the proper enum type to store the op 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26432>
 2023-12-07 14:40:24 +00:00
Yonggang Luo 72e30c8853 treewide: Avoid use align as variable, replace it with other names 
align is a function and when we want use it, the align variable will shadow it
So replace it with other names

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25997>
 2023-12-07 02:30:53 +00:00
Faith Ekstrand 09fc5e1c4d nir: Split has_[su]dot_4x8 bits into regular and _sat versions 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
 2023-12-06 23:15:33 +00:00
Faith Ekstrand e3ff5a3b0e intel/vec4: Use MESA_PRIM_* instead of GL_* 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24821>
 2023-12-05 23:12:32 +00:00
Caio Oliveira d9565a0e66 intel/compiler: Remove the linking step in intel_clc 
A previous patch already removed individual compilation of the inputs,
by simply concatenating the files. This patch removes the linking of
the remaining single object that's compiled.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26458>
 2023-12-05 11:48:25 +00:00
Caio Oliveira d9e49ce194 intel/compiler: Fix memory leaks in intel_clc 
Avoids failures when using Address Sanitizer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26458>
 2023-12-05 11:48:25 +00:00
Caio Oliveira db9111bb87 intel/compiler: Use single variable instead of dynarray 
A previous change concatenated multiple SPIR-V inputs to be
compiled together, so we have a single clc_binary to work on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26458>
 2023-12-05 11:48:25 +00:00
Caio Oliveira 73276c1ece intel/compiler: Refactor program exit in intel_clc 
Move the clean up code (at the moment just ralloc_ctx) into
a single place at the end.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26458>
 2023-12-05 11:48:25 +00:00
Jordan Justen 064bdecb36 intel/compiler: Define XE2 compiler enum 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Caio Oliveira bbb12dbbf9 intel/compiler: Add a few tests to opt_predicated_break 
v2 (idr): Fix expectations BottomBreakWithContinue. opt_predicated_break
will remove the IF and make the CONTINUE predicated.

v3 (idr): Temporarily disable the one test that fails.

v4 (idr): Free strings allocated by open_memstream. Fixes gitlab CI
failures in debian-testing-asan.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00