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8344 Commits

Author SHA1 Message Date
Caio Oliveira e21359ed0e intel/compiler: Create struct for TCS thread payload 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira 73920b7e2f intel/compiler: Use FS thread payload only for FS 
Move the setup into the FS thread payload constructor.  Consolidate
payload setup for that in brw_fs_thread_payload.cpp file.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira dab66d20a7 intel/compiler: Make a type for Thread Payload and FS variant 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Jordan Justen 582bad0256 intel/devinfo: Add MTL platforms enums and intel_device_info_is_mtl() 
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18482>
 2022-09-13 00:30:22 +00:00
Tapani Pälli 40c2e0a317 intel/compiler: fix assert from ver to verx10 
Fixes: 027b8b4249 ("intel/compiler: Add helper for barrier message payload setup for gfx >= 125")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18546>
 2022-09-12 19:03:17 +00:00
Jordan Justen af8ab4a889 intel/compiler: Use builder to allocate fs regs for gs control data bits 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18537>
 2022-09-12 10:00:28 -07:00
Caio Oliveira 00b8f9a3a6 intel/compiler: Use builder to allocate fs regs for TCS store output 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18537>
 2022-09-12 10:00:18 -07:00
Oleksii Bozhenko f350b78b73 anv: Allow aliasing with modifiers for WSI images 
Ignore ALIAS_BIT when format comes from WSI because
we have the ability to bind the MEMORY_BINDING_PRIVATE
from the other WSI image.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7019

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18347>
 2022-09-12 10:44:38 +00:00
Caio Oliveira 027b8b4249 intel/compiler: Add helper for barrier message payload setup for gfx >= 125 
CS-like and TCS control barriers converged in gfx >= 125, so use a
common helper for the message payload setup.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18362>
 2022-09-09 09:35:08 -07:00
Caio Oliveira 55db3aaa3a intel/compiler: Create fs_visitor::emit_tcs_barrier() 
Allow us to implement this in brw_fs_visitor.cpp, which then will
let us deduplicate code between the CS-like barrier and the TCS
barrier in a later patch.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18362>
 2022-09-09 09:35:08 -07:00
Kenneth Graunke 19fc870ac6 intel/compiler: Use subgroup invocation for ICP handle loads 
When loading a TCS or GS input, we generate some code to read the URB
handle for a particular input control point (ICP handle), which often
involves indirect addressing due to a non-constant vertex.

For example:

   mov(8) vgrf148+0.0:UW, 76543210V
   shl(8) vgrf149:UD, vgrf148+0.0:UW, 2u
   shl(8) vgrf150:UD, vgrf145:UD, 5u
   add(8) vgrf151:UD, vgrf150:UD, vgrf149:UD
   mov_indirect(8) vgrf147:UD, g2:UD, vgrf151:UD, 96u

Unfortunately, the first load with 76543210V is considered a partial
write because the 8 channels of 16-bit UW data doesn't fill an entire
register, and we can't allocate VGRFs at sub-register granularity.

This causes none of the above math to be CSE'd, even though the first
two instructions are common to *all* input loads, and the rest may be
reused sometimes as well.

To work around this, we stop emitting 76543210V to a temporary, and
instead use nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION], which
already contains this value, and is unconditionally set up for us.
With all input loads using the same register for the sequence, our
CSE pass is able to eliminate the rest of the common math.

shader-db results on Tigerlake:

   total instructions in shared programs: 20748243 -> 20744844 (-0.02%)
   instructions in affected programs: 73410 -> 70011 (-4.63%)
   helped: 242 / HURT: 21
   helped stats (abs) min: 1 max: 37 x̄: 14.17 x̃: 15
   helped stats (rel) min: 0.17% max: 19.58% x̄: 6.13% x̃: 6.32%
   HURT stats (abs)   min: 1 max: 4 x̄: 1.38 x̃: 1
   HURT stats (rel)   min: 0.18% max: 1.31% x̄: 0.58% x̃: 0.58%
   95% mean confidence interval for instructions value: -13.73 -12.12
   95% mean confidence interval for instructions %-change: -6.00% -5.19%
   Instructions are helped.

   total cycles in shared programs: 785828951 -> 785788480 (<.01%)
   cycles in affected programs: 597593 -> 557122 (-6.77%)
   helped: 227 / HURT: 13
   helped stats (abs) min: 6 max: 624 x̄: 182.19 x̃: 185
   helped stats (rel) min: 0.24% max: 18.22% x̄: 7.85% x̃: 7.80%
   HURT stats (abs)   min: 2 max: 153 x̄: 68.08 x̃: 36
   HURT stats (rel)   min: 0.03% max: 7.79% x̄: 2.97% x̃: 1.25%
   95% mean confidence interval for cycles value: -182.55 -154.71
   95% mean confidence interval for cycles %-change: -7.84% -6.69%
   Cycles are helped.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18455>
 2022-09-08 15:12:41 +00:00
Iván Briano 92ee2e6b64 anv: pipelineStageCreationFeedbackCount is allowed to be 0 
Fixes: 6601e5d6fc ("anv: implement VK_EXT_pipeline_creation_feedback")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18451>
 2022-09-07 10:49:29 -07:00
Tapani Pälli d276ad4520 intel/compiler: implement Wa_14014595444 for DG2 
According to the workaround, we should setup MLOD as parameter
4 and 5 for the sample_b message.

v2: only SAMPLE_B, not SAMPLE_B_C (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18408>
 2022-09-07 05:44:56 +00:00
Tapani Pälli f32ac1d30b anv: implement Wa_14015946265 for DG2 
SOL unit issues, wa is to send PC with CS stall after SO_DECL.

v2: emit also in genX_gpu_memcpy (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18409>
 2022-09-07 04:38:05 +00:00
Lionel Landwerlin 492761ab8d anv: add a new NO_LOCAL_MEM allocation flag 
We found a perf regression with 9027c5df4c ("anv: remove the
LOCAL_MEM allocation bit") which seems to be that we over subscribe
local memory, leading i915 to swap things in/out too much.

This change avoid putting buffers in local memory if they are not
allocated from a DEVICE_LOCAL heap.

Maybe we can revisit this later if i915 is better able to deal with
more buffers in local memory.

v2: Remove implicit_css from anv_bo when not in lmem (Ivan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9027c5df4c ("anv: remove the LOCAL_MEM allocation bit")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7188
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18395>
 2022-09-06 18:24:00 +00:00
Lionel Landwerlin 9194952e70 hasvk: expose VK_EXT_depth_clamp_zero_one 
Simple enough to expose on hasvk.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18372>
 2022-09-05 06:19:47 +00:00
Lionel Landwerlin a6de9dabf6 anv: enable EXT_depth_clamp_zero_one 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18372>
 2022-09-05 06:19:47 +00:00
Lionel Landwerlin 7e282694ed anv: remove non present field in upstream spec 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18397>
 2022-09-02 23:45:21 +00:00
David Heidelberg 250c684750 ci: uprev piglit 2022-08-30 
Acked-by: Juan A. Suarez <jasuarez@igalia.com>  # for broadcom
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>  # for zink
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18318>
 2022-09-02 20:15:28 +00:00
Marcin Ślusarz 9701b9098f anv: enable EXT_mesh_shader 
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz d5dedecfe7 anv: implement draw calls for EXT_mesh_shader 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz 637063ffc6 anv: implement EXT_mesh_shader 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz b3354afd89 anv: replace VK_SHADER_STAGE_[TASK|MESH]_BIT_NV with VK_SHADER_STAGE_[TASK|MESH]_BIT_EXT 
They have the same numerical values, so nothing changes.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz 9cefaa9b6d anv: check EXT_mesh_shader whenever NV_mesh_shader is checked 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz 2e1b96bb1b intel/compiler: implement EXT_mesh_shader 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Lionel Landwerlin 802fa57274 anv/hasvk: tweak loading failure messages 
We don't want to print out too many :

  MESA: error: ../src/intel/vulkan/anv_device.c:769: anv does not support Intel(R) HD Graphics (HSW GT1); use hasvk (VK_ERROR_INCOMPATIBLE_DRIVER)

whenever anv is not able to load on a HSW device. Similarly hasvk
should not print error on anything gfx9+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke bc68e7b564 anv: Remove anv_batch_emit_reloc and just open-code it 
We don't need the relocation offsets anymore, and just want to pin the
BO, and combine the address into a uint64_t.  We can just open code
those two things; it's actually less code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 479a999637 anv: Inline write_reloc into the only remaining caller 
This is writing an address and clflushing, but it's not really about
execbuf relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke b4677718f3 anv: Drop offset from anv_reloc_list_append 
No longer used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 02fed5bb32 anv: Make a helper function for pinning a state pool's BOs 
A bit less duplicated code, though with all the success checking, it
doesn't actually save us a whole lot.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke fde5c903c0 anv: Delete has_bindless_images and has_bindless_samples flags 
These are always true now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 9cb57c9a7a anv: Delete has_a64_buffer_access flag 
It's always true.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke c5f7e1f5b4 anv: Delete relocation support from batch submission 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 3fd4a294f5 anv: Delete wrapper BOs for relocations 
These were only used in the non-softpin case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 7b7381e8d7 anv: Delete anv_reloc_list_add() 
We don't need the offset to write a relocation at any longer, so all
it does is call anv_reloc_list_add_bo() at this point.  Just use that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 4b5c29bad0 anv: Delete softpin checks 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 215b1b69cb anv: Delete use_relocations flag 
There are no relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 97b98dcea9 anv: Drop state pool relocation munging 
Now that the state pool's center is always 0, this is not needed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 8cfe23a1e1 anv: Delete "back" allocation from anv_block_pool 
This was only used with relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 8fcaf1b921 anv: Delete relocation support from anv_block_pool 
We no longer use relocations.

v2: silence fedora builder warning

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 5d3fc2e091 anv: Delete "back" allocation from state pool 
This was only used with relocations, which no longer happen.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 05adcd1d0f anv/tests: Don't use relocations in a test case 
We won't support relocations shortly.

v2: Deal with softpin padding requirement (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Lionel Landwerlin 936ec9caae anv/tests: remove back allocation tests 
We'll remove driver code for this in the following commits.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke f34975cdf9 anv: Delete shader constants UBO from descriptor sets 
We now always softpin and use the load_global_constant case, so there's
no need to set up a UBO for NIR constants.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 7abb6f8e72 anv: Delete batch buffer growing code. 
This was only needed on Haswell and older due to the kernel command
parser not allowing us to chain batches.  anv no longer support this.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 428f07d906 anv: Delete image param support. 
This was only used prior to Skylake, which anv no longer supports.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 3daeb22735 anv: Drop checks for version 8 or 9 
anv no longer supports versions below this.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Kenneth Graunke 8dcca7f47f anv: Fail to create a device on ver < 9 
These are now only supported by hasvk.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Lionel Landwerlin a659819f79 anv: remove unused gfx7 code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00
Lionel Landwerlin 1a77f83c2b anv: remove support for gfx7/8 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
 2022-09-02 09:40:46 +00:00