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Author SHA1 Message Date
Jason Ekstrand
2e7656ae2f intel/eu: SVB writes only happen on Gen6 
It's a Gen6 XFB thing.  It's never used for anything else so there's no
point in having a target cache switch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
0421690f83 intel/compiler: add restrictions related to coarse pixel shading 
v2: Update to BITSET_TEST()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
81f369c93b intel/compiler: add coarse pixel offset on Gfx12.5+ 
Gfx12.5 has a slightly different code path.

v2: Document the oddness

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
6d4070f3dd intel/compiler: add support for fragment coordinate with coarse pixels 
v2: Drop new internal opcodes (Jason)
    Simplify code (Jason)

v3: Add Z computation for coarse pixels

v4: Document things a little

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
a297061524 intel/compiler: add support for fragment shading rate variable 
v2: Drop old register type initializers (Jason)
    Simplify instruction snippet (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
b6332fc4a8 intel/compiler: handle coarse pixel in render target writes descriptors 
v2: Use the new inst->ex_desc field (Jason)

v3: Drop CPS LoD compensation from sampler messages (Lionel)

v4: Drop useless uses_rate_shading (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
d665c2dcf0 intel/compiler: use existing helpers to pull bits of descriptors 
v2: Use new RT descriptor helper

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
64551610d1 intel/compiler: rework message descriptors for render targets 
Render target message descriptors are slightly different from the
dataport ones. In particular the msg_type field is on bits 14:17 for
RT while bits 14:18 for DP.

v2: Drop unused send_commit_msg field in brw_fb_write_desc() (Ken)

v3: Rebase on top renaming (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
dabaaaf6c7 intel/compiler: make sure we keep the lowest dispatch limit 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
4dcfb18a82 intel/decoder: decode CPS_STATE 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
b1622af394 intel/genxml: Add coarse pixel shading instructions 
v2: Add Gen12.5

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin
bbfc959d03 intel/dev: printout correct subslice/dualsubslice name 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Rob Clark
f3d2fade82 freedreno: Fix TC last_fence optimization 
Grabbing the fence value in fd_fence_repopulate() without waiting on
fd_submit_fence::ready doesn't work with async flushes, since we are
waiting for the first flush to complete (ie. we don't have the kernel-
side fence value yet).  Just simplify it and make the "repopulated"
fence delagate to the original fence.

Fixes: e9a9ac6f77 ("freedreno/drm: Async submit support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4726
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
 2021-05-02 15:17:25 +00:00
Rob Clark
c554757bc2 freedreno/drm: Initialize control->fence 
Don't rely on getting a zero'd out buffer, we could hit the bo-cache.

Fixes: 7dabd62464 ("freedreno/drm: Userspace fences")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
 2021-05-02 15:17:25 +00:00
Vasily Khoruzhick
636a7cf84b lima: switch resource to linear layout if there's to many full updates 
Overwriting entire resource multiple times indicates streaming and in this
case it's more efficient to use linear layout to avoid expensive linear->tiled
conversions.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10572>
 2021-05-02 14:55:13 +00:00
Vinson Lee
d6356b81a4 glx: Fix macOS build. 
In file included from ../src/glx/apple/apple_glx_context.c:49:
../src/glx/glxclient.h:56:10: fatal error: 'loader.h' file not found
         ^~~~~~~~~~

Fixes: 1cb664c15c ("glx: s/dri_message/glx_message/")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4702
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10568>
 2021-05-02 14:16:07 +00:00
Bastian Beranek
960c86d678 glx: Assign unique serial number to GLXBadFBConfig error 
Since commit f39fd3dce7 a new GLX error is issued in case context creation
fails. This broke wine on certain hardware: While wine installs an error handler
to ignore this kind of error, it does not function because it expects the
dpy->request serial number of the error to be incremented since the installation
of the handler.

Workaround this by artificially increasing the request number. This also
guarantees a unique serial number for the error.

Fixes: f39fd3dce7
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3969
Signed-off-by: Bastian Beranek <bastian.beischer@rwth-aachen.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10565>
 2021-05-02 00:36:03 +00:00
Ilia Mirkin
3326861f4f nv50: add indirect compute support 
There's no hardware support for anything indirect, so just read the
parameters out.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
b53b96a86a nv50: add support for doing membars 
This requires an address that's safe to read from.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
f451854f39 nv50: add remapping of buffers/images into unified space 
This allows us to use up to 15 images or buffers (but not both). GL
supports the concept of combined resource maximums though.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
58d47ca324 nv50: add compute invocations counter 
This is a purely software counter alongside the other hardware counters
for ease of use and consistency. However we have to make room for it in
the allocated query space. Use this opportunity to make the nv50 queries
work like the nvc0 ones in terms of space allocation.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
bd2f14a5ea nv50/ir: add lowering for shared atomics 
This is best-effort for pre-nva0 ... works with a single invocation,
i.e. no locking.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
6b1a526ac5 nv50/ir: add surface op lowering 
This handles BUFQ, SUQ, as well as all the various texture types and
formats, driven by data supplied by the driver (and shader itself).

TODO:
 - 2d linear surfaces
 - format via key for writeonly

These will be included in a later change. ES3.1 doesn't require
writeonly, and it's very hard to generate a 2d linear surface.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
67f98497af nv50: pass surface/buffer parameters to shader via aux buffer 
These are needed to implement things like imageSize() as well as feed
data into lowering logic for various access types not handled by the
hardware.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
e762061127 nv50/ir: optimize shift of 0 bits 
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
dbdc2b160c nv50/ir: wipe any info about memory when seeing a locking op 
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
1cf864ef9e nv50/ir: mark ATOM as having 3 arguments 
Otherwise the final argument doesn't get emitted for CAS in the nv50
emitter.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
348db055dd nv50/ir: "zero" register does not work with g[] memory 
Evidence suggests that having it anywhere, even as a regular e.g. atom
argument, causes issues.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
21f9b1cbe7 nv50/ir: refine limitation on load/store loading offsets, include atomics 
Note that shared memory loads can actually do offsets. The restrictions
vary by generation, this will be added in a later change.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Ilia Mirkin
c95d2a86d3 nv50/ir: offset accesses to shared memory 
Ideally this should include the size of the inputs as well. This will be
updated when we add support for kernels which take actual inputs.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
 2021-05-01 20:04:21 +00:00
Marek Olšák
967757a208 gallium+(u_threaded,r300,r600,radeonsi): move transfer offset into pipe_transfer 
Let's use the 4 bytes of unused padding usefully in pipe_transfer.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
 2021-05-01 17:38:42 +00:00
Marek Olšák
6005b86893 gallium: remove 4 bytes from pipe_transfer 
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
 2021-05-01 17:38:42 +00:00
Marek Olšák
00c30dad78 gallium: renumber PIPE_MAP_* enums to remove holes 
We could change the type into 16 bits if needed.

PB_USAGE flags need to match PIPE_MAP flags due to static assertions.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
 2021-05-01 17:38:42 +00:00
Rob Clark
22575a7b11 freedreno/ci: Update piglit skips/fails 
Add spec@arb_pixel_buffer_object@texsubimage cube_map_array pbo to a530
fails for the same reason as spec@arb_texture_cube_map_array@texsubimage cube_map_array
(it is sometimes triggering gpu hangs that cause other flakes).

And remove two a630 xfails that started showing up as UnexpectedPass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
 2021-05-01 08:47:50 -07:00
Rob Clark
928453ccb2 freedreno/ci: Mark client_wait_sync_finish as flake 
This one has shown up a couple times since fd/go-fast, I'm still trying
to reproduce/debug.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
 2021-05-01 08:47:50 -07:00
Rob Clark
bc3f66311d freedreno: Flush resources harder 
pctx->flush_resource() has the same expectations that the resource can
be shared with an external client as pctx->flush(), but without the
convenience of a fence to know *when* the resource must be visible to
that external client.  So we need to ensure the batch is flushed all the
way to the kernel so that implicit-sync can do it's job.

Fixes: e9a9ac6f77 ("freedreno/drm: Async submit support")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
 2021-05-01 08:46:27 -07:00
Rob Clark
5181f40670 freedreno/drm: Allow FD_BO_PREP_FLUSH without _NOSYNC 
This provides the upper layer (gallium, etc) a way to ensure that
rendering involving the bo has been flushed all the way to the kernel.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
 2021-05-01 08:46:27 -07:00
Rob Clark
dbdc979320 freedreno: Remove samples-per-tex tracking 
Looks like this was unused, and only served to segfault when unbinding
textures.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
 2021-05-01 08:46:27 -07:00
Rob Clark
9fa3312773 freedreno/ci: Isolate dEQP-EGL reset_context tests 
To reduce flakes, separate out the dEQP-EGL tests that are intentionally
triggering GPU hangs.  This avoids some kernel side issues with bad
handling of ringbuffer-full scenarios, causing innocent tests to flake.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10560>
 2021-05-01 02:37:05 +00:00
Rob Clark
cee1673684 ci: Add DEQP_CASELIST_INV_FILTER 
Inverts the match compared to DEQP_CASELIST_FILTER

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10560>
 2021-05-01 02:37:05 +00:00
Eric Anholt
ec7923bd97 ci/freedreno: Mark another recent piglit flake. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
 2021-04-30 16:47:09 -07:00
Eric Anholt
fc9ba9a911 ci/freedreno: Mark new flakes from the go-fast branch. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
 2021-04-30 16:47:02 -07:00
Eric Anholt
0987df6a3e ci/freedreno: Mark dEQP-EGL flakes reported on IRC since its introduction. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
 2021-04-30 16:44:20 -07:00
Icecream95
ab8e531cf0 panfrost: Fix viewport scissor for preload draws 
The max values are inclusive, so add 1 before aligning. This means
that a max of 32 will be aligned up to 64 then be decremented to 63.

Add a comment to the pan_fb_info struct to document maxx and maxy as
inclusive.

Fixes: 8ba2f9f698 ("panfrost: Create a blitter library to replace the existing preload helpers")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
 2021-04-30 22:24:58 +00:00
Icecream95
9910a14a1a panfrost: Remove incorrect comment 
The comment was wrong in its original location and is wrong here, just
remove it.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
 2021-04-30 22:24:58 +00:00
Dylan Baker
f03da01fe3 meson/vulkan: fix linkage on windows 
The current approach likley breaks icl and clang-cl, but it seems that
the problem isn't even really related to MSVC, but to Meson's Visual
Studio backend, as such, let's use link-whole unless we're using a
Visual Studio backend.

Fixes: 48d31a6280
       ("meson: link vulkan_util with link_whole on mingw")

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: James Park <jpark37@lagfreegames.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10506>
 2021-04-30 18:49:20 +00:00
Gustavo Padovan
d47c2af8d2 gitlab-ci: enable all 3 intel devices as manual in MR pipelines 
This uses the rule created by .test-manual-mr that enables experimental
devices in MR pipelines, but not for Marge.

The goal is to expose the devices to more possibility of testing before
we enable them automatically.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10405>
 2021-04-30 17:15:06 +00:00
Gustavo Padovan
c5e06bb894 gitlab-ci: rule anchor for experimental devices as manual in MRs 
We want to give developers the option to run their jobs on devices
that are still being stabilized in the CI infrastructure.

These jobs should be optional and not prevent merging from happening.

The is-forked-branch-or-pre-merge anchor was not being used anywhere,
so it was changed to is-forked-branch-or-pre-merge-not-for-marge to
create this new rule.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10405>
 2021-04-30 17:15:06 +00:00
Jason Ekstrand
b80720acb1 intel/isl: Fix isl_color_value_unpack to match the prototype 
The prototype uses a pointer and the actual function definition had an
array.  For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.

Fixes: 09ced65420 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
 2021-04-30 17:01:05 +00:00
Danylo Piliaiev
1201aa9332 ir3: do not move varying inputs that depend on unmovable instrs 
Not all varying fetches could be pulled into the start block.
If there are fetches we couldn't pull, like load_interpolated_input
with offset which depends on a non-reorderable ssbo load or on a
phi node, this pass is skipped since it would be hard to find a place
to set (ei) flag (beside at the very end).

We also don't have to manually set (ei) in such cases since a5xx and
a6xx do automatically release varying storage at the end.
Earlier gens need further testing, however they do not support
interpolateAt* functions at moment, so unless we would like to support
sample shading on them - they are fine.

Fixes crash in GTA V.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10483>
 2021-04-30 14:49:18 +00:00