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Author SHA1 Message Date
Alyssa Rosenzweig
d0fc23b7bd pan/mdg: Don't print explicit .rte 
Default round mode.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
9bd3ebf829 pan/mdg: Suppress most attribute tables 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
07740e78b4 pan/mdg: Don't print zero shifts 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
fa68c8bca9 pan/mdg: More concise RMU name 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
7752b09ade pan/mdg: Hide units behind MIDGARD_MESA_DEBUG=verbose 
Not usually interesting unless debugging bundling.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
93a176b6cf panfrost: Key blend shaders to the input types 
On Bifrost, fragment shaders might output either FP16 or FP32. The blend
shader will access the output as-is within the register, so depending on
the precision of the blend shader's logic, it may need to insert a
f2f16 or f2f32 conversion. This requires expanding the blend shader key.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
9df1d1306e pan/blend: Emit explicit conversions for all types 
Needed so we can mix and match.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
30423b0c36 panfrost/lower_framebufffer: Don't use i2imp 
Fails when converting from i2i8, which is possible.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
03e3e65cd4 panfrost: Assume lower_fragcolor has been called 
Allows us to clean up quite a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
28ac4d1e00 panfrost: Call nir_lower_fragcolor based on key 
We only want it to trigger if MRT is actually in use. This is a cheap
key (only require multiple variants for an obscure edge case) and avoids
the perf regression of using this pass which is needed for conformance.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
6a4482df98 panfrost/blend: Prepare for lower_fragcolor 
FRAG_RESULT_COLOR means something a bit different.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
120dd92e86 panfrost/blend: Distribute to_c_factor 
Easier to understand, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
613722e046 panfrost/blend: Workaround a v7 implementation-detail 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
392bf00019 panfrost/blend: Fix outdated comments 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
86b0eddf2b pan/lower_blend: Rename is_bifrost->scalar 
Don't leak ISA details.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
f5211fcbed pan/lower_blend: Use NIR helpers 
Deletes a bunch of indentations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
5fc1aed036 pan/lower_blend: Clean up type size handling 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
dad599f15e panfrost: Don't clobber RT0 if RTn is disabled 
Fixes: a124c47b9f ("panfrost: Fix NULL derefs in pan_cmdstream.c")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
5268a8500a panfrost: Minor cleanup of blend CSO 
No need to cast.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
3968f03754 panfrost: Support alpha_to_one 
Gets rid of a bogus assert in the blend CSO create.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
a368cc022d panfrost: Make comment less confusing 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
c6bb55ffcf pan/bi: Lower 8-bit fragment input 
Same reasons/technique as fragment output lowering, just need the NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
3cc6a4c5d0 pan/bi: Handle swizzles in i2i8 
Otherwise they get copypropped away.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
e180374ab1 pan/bi: Add single-component 8-bit mkvec lowering 
So we can implement scalar i2i8.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
ba17342a1f pan/bi: Handle different sizes of LD_TILE 
v2: Fix overflow.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Alyssa Rosenzweig
f412801768 pan/bi: Track dual-src blend type 
Will be needed for fp16 outputs. I am acutely aware dual-src blending is
broken on Bifrost right now anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
 2021-05-04 20:04:03 +00:00
Yiwei Zhang
e44b4feb33 venus: query extended resource info from gralloc 
Creating Android swapchain image from gralloc buffer requires to use
VkImageDrmFormatModifierExplicitCreateInfoEXT. To fill the struct info,
we need to query extended resource info from gralloc.

With the queried modifier from gralloc, we can ask the driver for the
plane count of the given format and modifier pair.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10553>
 2021-05-04 19:52:13 +00:00
Eric Anholt
a2efa2e833 tgsi: Mark the tgsi_exec_channel and tgsi_double_channel ALIGN16. 
We allocate them all align16, so mark the unions (and their container
structs) that way so the compiler can do aligned SSE load/stores.

glmark2 -b loop FPS +0.197265% +/- 0.117633% (n=1906)

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10604>
 2021-05-04 18:58:51 +00:00
Charlie Turner
1d418e79b8 radv: Add a STONEY baseline for dEQP. 
See:
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9286188
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297109
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297110

v2.
  - Clarify that the dEQP-VK.texture.explicit_lod.2d tests are skipped
  due to slow APU-based STONEY test devices.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10559>
 2021-05-04 16:42:57 +00:00
Iago Toral Quiroga
f099fc3e07 v3d: choose a larger CSD supergroup size if possible 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
 2021-05-04 15:53:23 +00:00
Iago Toral Quiroga
3ce249e65e broadcom/common: move CSD supergroup sizing to a common helper 
We want to use this in GL too.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
 2021-05-04 15:53:23 +00:00
Iago Toral Quiroga
afc33a7430 v3dv: limit supergroup size in presence of TSY barriers 
When a TSY barrier is hit, the entire supergroup will be synchronized.
If the supergoup is large and uses all available QPU threads it would
mean that we would sychronize and stall all running threads until all
of them reach the barrier, which may be inefficient.

This patch makes it so that if the compute shader has any such barriers
we limit the supergroup size so each supergroup only takes half of the
QPU threads available at most, so that if one supergroup hits a
barrier we have at least one other supergroup we can run, reducing
idle QPU time.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
 2021-05-04 15:53:23 +00:00
Iago Toral Quiroga
f514280524 broadcom/compiler: track if a shader has control barriers in prog_data 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
 2021-05-04 15:53:23 +00:00
Iago Toral Quiroga
2e0f6e5705 v3dv: choose a larger CSD supergroup size if possible 
Each supergroup executes a number batches. Each batch has 16 elements
(one per QPU lane), except possibly the last batch which might be
incomplete. Until now, we packed a single workgroup in each supergroup,
which can lead to more incomplete batches and less efficient use
of the QPUs depending on the configuration of workgroups being dispatched.

This patch computes a number of workgroups per supergroup so that
we reduce or completely eliminate incomplete batches if possible.

It should be noted however, that TSY barriers act on supergroups,
so larger supergroups lead to larger syncpoints on barriers too.
A follow-up patch will try to find a good balance for compute shaders
that use such barriers.

This improves performance of the Sascha Willem's computecloth demo
by ~13%.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
 2021-05-04 15:53:23 +00:00
Iago Toral Quiroga
aebb47b7d1 compiler/nir: add a divergence analysis option for non-uniform workgroup id 
The V3D hardware allows us to pack multiple workgroups together to avoid
wasting execution lanes in shader cores.

For example, if we dispatch 16 workgroups with a local size of 1 element, we
can pack all 16 workgroups in a single 16-wide dispatch where each lane
executes a different workgroup, instead of 16 1-wide dispatches.

When we do this, we don't have a uniform workgroup id any more.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
 2021-05-04 15:53:23 +00:00
Caio Marcelo de Oliveira Filho
caf9fb1a10 intel/compiler: Remove unused exported functions 
Now that all drivers are using brw_cs_get_dispatch_info() we can
remove one function (which is now unused) and reduce the scope of the
other.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Caio Marcelo de Oliveira Filho
313c80c158 i965: Use brw_cs_get_dispatch_info() 
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Caio Marcelo de Oliveira Filho
279acf1031 anv: Use brw_cs_get_dispatch_info() 
And since right_mask is already provided as part of dispatch_info,
just use that instead of storing it.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Caio Marcelo de Oliveira Filho
59cbd50bfa iris: Use brw_cs_get_dispatch_info() 
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Caio Marcelo de Oliveira Filho
5cc758558d intel/compiler: Add common function for CS dispatch info 
We have this small calculations repeated in each Intel driver, so move
them to a single place to be reused.  Also includes "right_mask" since
is always used in the same context and depends on the dispatch info
values.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Caio Marcelo de Oliveira Filho
7cc846788c nir: Remove now unnecessary conditions from emit_load/store helpers 
The mode one was used before 0bc5a829dd ("nir: Remove shared support from
lower_io").

The others were used before 5f7c7c9a7f ("nir: add src and dest types
to all IO loads and stores for mediump").

All conditions now are always true, so drop them.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10533>
 2021-05-04 06:33:24 -07:00
Boris Brezillon
693ae0d3e9 panfrost/ci: Run the full deqp-gles3 testsuite 
We recently added 5 more VIM3s to the lavalab, this should be more than
enough to run the full GLES 3.0 testsuite on G52.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10614>
 2021-05-04 11:22:15 +00:00
Erik Faye-Lund
a2140e29c5 docs: update gallium doxygen docs 
Gallium's background as a Tungstend Graphics technology is no longer
significant; it's a historical detail. Besides, since Tungsten Graphics
were acquired by VMware more than a decade ago, the website no longer
exists.

While we're at it, replace the docs link with a link to the mesa docs,
and point to archive.org copy of the Tungsten Graphics paper.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2770
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10452>
 2021-05-04 08:38:45 +00:00
Gert Wollny
a199697642 nir/opt_algebraic: optimizations for add umax/umin with zero 
For unsigned comparisons with zero these ops can be eliminated.

v2: Add comparison optimizations with -1 (Rhys Perry)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10583>
 2021-05-04 09:33:32 +02:00
Erik Faye-Lund
301ceab7ce lavapipe: consistently use nir macros 
NIR provides two helper macros to run transformation passes correctly,
NIR_PASS() and NIR_PASS_V(). So far we've seemingly been a bit haphazard
about when to use them.

Let's correct that, and consistently use the NIR helpers here. This
helps us in two ways:

1. We now run nir_validate_shader after each pass, ensuring we didn't
   break the shader
2. We now respect the NIR_PRINT environment variable for all NIR passes,
   making debugging much less surprising.

In addition, we had an OPT()-macro that doesn't seem to provide much
help other than to hiding some trivial details. But they make our code
different to other users of NIR, which doesn't seem ideal. So let's drop
that macro while we're at it.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10585>
 2021-05-04 07:18:55 +00:00
Samuel Pitoiset
53fe74bbb1 radv: implement RADV_FORCE_VRS for the LLVM backend 
Just to make it consistent compared to ACO.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10432>
 2021-05-04 08:23:56 +02:00
Marek Olšák
48d2ac4e88 util: fix (re-enable) L3 cache pinning 
cores_per_L3 was uninitialized, so it was always disabled.
Remove the variable and do it differently.

Fixes: 11d2db17c5 - util: rework AMD cpu L3 cache affinity code.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>
 2021-05-04 01:02:07 -04:00
Marek Olšák
9b58e31f2d util: print CPU caps in release builds too 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>
 2021-05-04 01:02:07 -04:00
Dave Airlie
897bcc1e6b i965: drop old brw ff gs code. 
This isn't needed anymore.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
 2021-05-04 03:39:45 +00:00
Dave Airlie
8d5f36fe14 i965: port fixed function geom shader to use compiler paths 
This just moves to the common code in the compiler.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
 2021-05-04 03:39:45 +00:00