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Author SHA1 Message Date
Faith Ekstrand de5bc9128c intel/vec4: Stop passing around nir_dest 
We want to get rid of nir_dest so back-ends need to stop storing it
in structs and passing it through helpers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
 2023-08-14 21:22:53 +00:00
Lionel Landwerlin 7ec12b537a anv: don't try to access dynamic buffers from surface states 
Even with direct descriptors, our current implementation works by
doing A64 messages to read/write dynamic buffers. This is so that we
can apply the sliding range view of the descriptor while having
robustness support.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 06dfd216d3 ("anv: add direct descriptor support to apply_layout")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24256>
 2023-08-14 07:27:16 +00:00
Faith Ekstrand 0ec7b8455e nir: Drop nir_ssa_dest_init_for_type() 
Replace it with a new nir_def_init_for_type()

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24658>
 2023-08-13 17:12:52 +00:00
Faith Ekstrand d2c4749986 nir: Drop more instances of nir_ssa_dest_init() 
Catching the cases that Coccinelle missed.  Mostly in C++ files using
gtest which causes Coccinelle to just give up and walk away.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24658>
 2023-08-13 17:12:52 +00:00
Faith Ekstrand ed9affa02f nir: Drop most instances of nir_ssa_dest_init() 
Generated using the following two semantic patches:

    @@
    expression I, J, NC, BS;
    @@

    -nir_ssa_dest_init(I, &J->dest, NC, BS);
    +nir_def_init(I, &J->dest.ssa, NC, BS);

    @@
    expression I, J, NC, BS;
    @@

    -nir_ssa_dest_init(I, &J->dest.dest, NC, BS);
    +nir_def_init(I, &J->dest.dest.ssa, NC, BS);

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24658>
 2023-08-13 17:12:52 +00:00
Alyssa Rosenzweig 09d31922de nir: Drop "SSA" from NIR language 
Everything is SSA now.

   sed -e 's/nir_ssa_def/nir_def/g' \
       -e 's/nir_ssa_undef/nir_undef/g' \
       -e 's/nir_ssa_scalar/nir_scalar/g' \
       -e 's/nir_src_rewrite_ssa/nir_src_rewrite/g' \
       -e 's/nir_gather_ssa_types/nir_gather_types/g' \
       -i $(git grep -l nir | grep -v relnotes)

   git mv src/compiler/nir/nir_gather_ssa_types.c \
          src/compiler/nir/nir_gather_types.c

   ninja -C build/ clang-format
   cd src/compiler/nir && find *.c *.h -type f -exec clang-format -i \{} \;

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24585>
 2023-08-12 16:44:41 -04:00
Lionel Landwerlin 7cc2f23d53 anv: move genX(rasterization_mode) to gfx8_cmd_buffer.c 
Only used there.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:32 +00:00
Lionel Landwerlin 705840d417 anv: get rid of genX(emit_multisample) 
The initialization can be simplified and the real programming moved
over to genX_pipeline.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:32 +00:00
Lionel Landwerlin eef54f3175 intel/decoder: add options to decode surfaces/samplers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:32 +00:00
Lionel Landwerlin cf5ee0a0f7 anv: emit 3DSTATE_GS only once per pipeline 
Following 71ebd9b9d7, 3DSTATE_GS can be emitted as part of the
pipeline batch and as a dynamic state. Just do the latter.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 71ebd9b9d7 ("anv,hasvk: respect provoking vertex setting on geometry shaders")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:31 +00:00
Lionel Landwerlin 8689791e1f blorp: drop programming of 3DSTATE_(MESH|TASK)_SHADER 
We can disable the MESH/TASK stages by just using the CONTROL
instruction and keep the rest of the HW programmed as before.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:31 +00:00
Lionel Landwerlin 22c7ccb523 intel/decoder: constify some input parameters 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:31 +00:00
Tapani Pälli 92941ee84b anv: implement required PSS sync for Wa_18019816803 
According to WA description, we need to track DS write state
and emit a PSS_STALL_SYNC whenever that state changes.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18411>
 2023-08-11 07:15:48 +00:00
Tapani Pälli 419531c5d9 intel/blorp: add a new flag to communicate PSS sync need 
This is required for Wa_18019816803 when blorp emit DS state.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18411>
 2023-08-11 07:15:48 +00:00
Konstantin Seurer eaee792ea5 vulkan: Add a generated vk_properties struct 
Generates a physical device properties table to avoid dealing with pNext
chains in the driver. Based on vk_features.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24575>
 2023-08-11 02:53:47 +00:00
Lionel Landwerlin 6f694432e4 intel/fs: add variable for output of debug backend optimizer 
It can be useful to compare 2 runs with different compiler changes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24552>
 2023-08-10 06:39:57 +00:00
Lionel Landwerlin 0e244d56e3 intel/fs: track more steps with INTEL_DEBUG=optimizer 
One particular nice thing to have is the first generated backend IR
before validation. Especially if you made a mistake in the NIR
translation, you can at least look at it before validation tells you
off.

Then the last 2 steps of the optimize() function can be interesting to
look at.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24552>
 2023-08-10 06:39:57 +00:00
Lionel Landwerlin c87d5c67d9 anv: implement VK_EXT_pipeline_robustness 
v2:
 - Use vk_pipeline_robustness_state

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
 2023-08-09 09:03:45 +03:00
Lionel Landwerlin 9934613c74 anv/hasvk: track robustness per pipeline stage 
And split them into UBO and SSBO

v2 (Lionel):
 - Get rid of robustness fields in anv_shader_bin
v3 (Lionel):
 - Do not pass unused parameters around

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
 2023-08-09 09:00:12 +03:00
Lionel Landwerlin c4ec60e87d hasvk: remove descriptor array bounds checking 
Same reason as Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
 2023-08-09 09:00:12 +03:00
Lionel Landwerlin 059e82a469 anv: remove descriptor array bounds checking 
We cannot find anything in the Vulkan spec requiring this. D3D12 [1]
says it's undefined as long as it doesn't crash the OS :

   "Out of bounds indexing of any descriptor table from the shader
    results in a largely undefined memory access, including the
    possibility of reading arbitrary in-process memory as if it is a
    hardware state descriptor and living with the consequence of what
    the hardware does with that. This could produce a device reset, but
    will not crash Windows."

[1] : https://learn.microsoft.com/en-us/windows/win32/direct3d12/advanced-use-of-descriptor-tables#out-of-bounds-indexing

Found 2 titles affected by this change

Some pretty good results on Cyberpunk 2077 :

  Totals from 10285 (100.00% of 10285) affected shaders:
  Instrs: 7638709 -> 7517360 (-1.59%); split: -1.64%, +0.05%
  Cycles: 148047414 -> 148470916 (+0.29%); split: -0.83%, +1.12%
  Subgroup size: 112544 -> 112576 (+0.03%); split: +0.04%, -0.01%
  Spill count: 98 -> 90 (-8.16%)
  Fill count: 90 -> 82 (-8.89%)
  Max live registers: 495274 -> 479502 (-3.18%); split: -3.21%, +0.03%
  Max dispatch width: 87824 -> 91168 (+3.81%); split: +4.10%, -0.29%

  Gaining 297 shaders in SIMD16/32, loosing 16 SIMD32 shaders

Some not so good results on Strange Brigade :

  Totals from 4027 (100.00% of 4027) affected shaders:
  Instrs: 2080355 -> 2013880 (-3.20%); split: -3.20%, +0.01%
  Cycles: 25405149 -> 25170579 (-0.92%); split: -1.37%, +0.45%
  Max live registers: 167303 -> 168958 (+0.99%)
  Max dispatch width: 33264 -> 32496 (-2.31%)

  Loosing 96 SIMD16 shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
 2023-08-09 09:00:12 +03:00
Lionel Landwerlin 0e5b4b1b43 hasvk: fix null descriptor handling with A64 messages 
This replicates the same fix we did for Anv and null descriptors with
A64 messages from commit efcda1c530 ("anv: fix null descriptor
handling with A64 messages").

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
 2023-08-09 09:00:12 +03:00
Yonggang Luo d130c96bda util/treewide: Use alignas(x) instead __attribute__((aligned(x))) 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24571>
 2023-08-09 05:15:09 +00:00
Sagar Ghuge f575d4bc6f blorp: Implement blorp hooks to emit breakpoint 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
 2023-08-08 17:36:19 +00:00
Sagar Ghuge 49eabb9ea6 anv: Add GPU breakpoint before/after specific draw call 
This change allow us to insert the MI_SEMAPHORE_WAIT before/after
specific draw call. With GTX tool, we can always update the memory
address to unblock spinning wait.

v2:
- Make sure draw_call_count is thread-safe (Lionel)
- Add static inline helper (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
 2023-08-08 17:36:19 +00:00
Sagar Ghuge e5116e00ca intel: Add env variable to add break point on/before draw 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
 2023-08-08 17:36:19 +00:00
Jordan Justen 493e8c4b50 intel/genxml: Add filter_engines() to GenXml class 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>
 2023-08-08 08:58:36 +00:00
Jordan Justen 5e275d8a2b intel/genxml: Add GenXml class into intel_genxml module 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>
 2023-08-08 08:58:36 +00:00
Jordan Justen 6e54245d00 intel/genxml: Convert gen_pack_header to use ElementTree 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>
 2023-08-08 08:58:36 +00:00
Jordan Justen a8a50332a6 intel/genxml: Convert gen_bits_header to use ElementTree 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>
 2023-08-08 08:58:36 +00:00
Jordan Justen ef2f2ae765 intel/genxml: Split some genxml sorting code into a intel_genxml module 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>
 2023-08-08 08:58:36 +00:00
Jordan Justen 761bcc3716 intel/genxml: Align "Texture Coordinate Mode" naming 
Some older gens used '_' (underscore) while newer gens used a ' '
(space).

$ sed -i 's/Texture_Coordinate_Mode/Texture\ Coordinate\ Mode/' \
      src/intel/genxml/*.xml

The naming needs to be aligned for importing enums later on.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>
 2023-08-08 08:58:36 +00:00
Benjamin Cheng 4755276baf anv/video: copy from correct H264 scaling lists 
Vulkan defines the scaling lists according to the H264 ITU spec, which
only defines ScalingList8x8[0] and ScalingList8x8[1] for
non-444 formats.

Reviewed-by: Lynne <dev@lynne.ee>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24474>
 2023-08-08 03:21:39 +00:00
José Roberto de Souza d686cadfbf intel: Sync xe_drm.h and rename engine to exec_queue 
Sync with commit f16c04291100 ("drm/xe: Rename engine to exec_queue").
With that Iris and ANV had some major renames that were done manually
as there is to many "engine" in non-related code.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24476>
 2023-08-07 21:34:14 +00:00
Lionel Landwerlin f5074adeb5 anv: enable INTEL_DEBUG=nofc 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24510>
 2023-08-07 12:02:57 +03:00
Jordan Justen bfe4a0e744 intel/decoder: Make intel_spec_load_filename() have separate dir and name strings 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20889>
 2023-08-06 20:44:59 +00:00
Jordan Justen b4c8d2dc45 intel/decoder: Add intel_spec_load_common() 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20889>
 2023-08-06 20:44:59 +00:00
Jordan Justen 1d5535613e intel/decoder: Fix xml filename when verx10 % 10 is not 0 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20889>
 2023-08-06 20:44:59 +00:00
Kenneth Graunke 95db3e87fe intel/compiler: Fix sparse cube map array coordinate lowering 
Brown paper bag fix for my untested review feedback comments.

Cube array images use a coordinate of the form <X, Y, 6*Slice+Face>,
while cube array textures use a <X, Y, Slice, Face> style coordinate.

This code tried to convert one to the other, but instead of writing
Z / 6 and Z % 6, we tried to reuse our original division result.  What
we wanted was Z - (Z/6) * 6, but instead we botched it and wrote Z-Z*6
which produced...totally invalid cube faces.

Fixes: fe81d40bff ("intel/nir: add lower for sparse images & textures")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24481>
 2023-08-04 00:09:05 -07:00
Alyssa Rosenzweig 42ee8a55dd nir: Remove nir_alu_dest::write_mask 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:30 +00:00
Alyssa Rosenzweig 4828881e28 intel/vec4: Don't use legacy write mask 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:30 +00:00
Alyssa Rosenzweig 11fc4f969c intel: Collapse is_ssa checks 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:29 +00:00
Alyssa Rosenzweig 579bc1e72e treewide: Drop some is_ssa if's 
Via Coccinelle patch:

    @@
    expression x;
    @@

    -if (!x.is_ssa) {
    -...
    -}

and likewise with x->is_ssa, with invalid hunks manually filtered out.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:29 +00:00
Alyssa Rosenzweig 95e3df39c0 treewide: sed out more is_ssa 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:28 +00:00
Alyssa Rosenzweig a8013644a1 nir: Drop nir_alu_src::{negate,abs} 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:28 +00:00
Alyssa Rosenzweig ab0d878932 treewide: Remove more is_ssa asserts 
Stuff Coccinelle missed.

   sed -i -e '/assert(.*\.is_ssa)/d' $(git grep -l is_ssa)
   sed -i -e '/ASSERT.*\.is_ssa)/d' $(git grep -l is_ssa)

+ a manual fixup to restore the assert for parallel copy lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:28 +00:00
Alyssa Rosenzweig 5fead24365 treewide: Drop is_ssa asserts 
We only see SSA now.

Via Coccinelle patch:

    @@
    expression x;
    @@

    -assert(x.is_ssa);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:28 +00:00
Alyssa Rosenzweig d559764e7c nir: Remove nir_alu_dest::saturate 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
 2023-08-03 22:40:28 +00:00
Yonggang Luo 86bcc90c0e intel/compiler,intel/blorp,intel/vulkan: decouple vulkan driver and compiler from gallium 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24438>
 2023-08-03 22:00:15 +00:00
Yonggang Luo 9eb8a0b16a intel/brw: Define and use BRW_SWIZZLE_* instead of SWIZZLE_* 
This is for avoid #include "program/prog_instrunction.h" in intel/brw code

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24438>
 2023-08-03 22:00:15 +00:00