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Author SHA1 Message Date
Jason Ekstrand dc6794ec24 anv: Rework depth/stencil early return in anv_get_format_plane 
The comment about modifiers is bogus because we check the modifier
before this check and return early.  Also, there's no reason why we need
to check the requested aspect when we could check the format itself.
anv_image_aspect_to_plane will ensure that the requested aspect is one
that actually exists.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
 2021-08-09 16:07:23 +00:00
Jason Ekstrand 4518ae8284 anv: Rename anv_get_format_plane to anv_get_format_aspect 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
 2021-08-09 16:07:23 +00:00
Jason Ekstrand 5dd55b0881 anv/blorp: Use the isl_surf for computing level_width/height in anv_image_ccs_op 
Don't manually monkey around with the denominator scales.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
 2021-08-09 16:07:23 +00:00
Jason Ekstrand 9a267be039 anv/blorp: Drop some can_ycbcr checks 
Vulkan allows us to, in theory, support ycbcr on single-plane formats if
the client really wants it.  Also, these functions should work on a
multi-plane color image as long as the client specifies the right
aspect.  This gets rid of our usage of can_ycbcr outside of anv_image.c.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
 2021-08-09 16:07:23 +00:00
Jason Ekstrand bf87b9ad81 nouveau: Use nir_lower_tex for projectors 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11826>
 2021-08-09 15:19:36 +00:00
Mike Blumenkrantz ec66c58138 nir: add imm_vec3 to round these out 
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12253>
 2021-08-09 14:45:30 +00:00
Bas Nieuwenhuizen 02b6015945 radv: Allocate space for inline push constants. 
In the compute dispatch path we do not allocate a huge amount
of space to cover everything so the individual functions have to
allocate. This was missing here, causing a hang in Cyberpunk when
accessing the system menu at some locations with thread tracing
enabled.

Fixes: bd1186572f ("radv: add support for push constants inlining when possible")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12271>
 2021-08-09 14:26:21 +00:00
Bas Nieuwenhuizen b2b1e8e40a radv: Use correct signedness in misalign test. 
Lots of the MAX2 args end up subtracting two unsigned numbers, which
blows up when the result is negative.

Fixes: 4c99d6ff54 ("radv: flush L2 for images affected by the pipe misaligned issue on GFX10+")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12272>
 2021-08-09 14:03:37 +00:00
Boris Brezillon 06fc6e46f0 panfrost: Fix pan_blitter_emit_bifrost_blend() 
If we return inside a pan_pack() the descriptor packing doesn't happen.

Cc: mesa-stable
Fixes: 8ba2f9f698 ("panfrost: Create a blitter library to replace the existing preload helpers")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12239>
 2021-08-09 13:47:02 +00:00
Juan A. Suarez Romero 91a5afcd5f v3d: print error on perfmon destroy error 
Print an error in case destroying the kernel perfmon fails.

Fixes CID 1489964: Error handling issues (CHECKED_RETURN).

v2:
 - Wrap line (Iago).

Fixes: 685281278e ("v3d: implement performance counter queries")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12280>
 2021-08-09 13:31:20 +00:00
Juan A. Suarez Romero d0e83b6174 broadcom/compiler: change current block on setting spill base 
The spill base setting instructions (which includes some uniforms) are
added in the entry block, not in the current block. When ldunif
optimization is applied, the cursor is pointing to instructions in the
entry block, but the current block is a different one. This leads to a
heap-buffer-overflow when going through the list of instructions
(detected by the address sanitizer).

Thus change the current block to entry block, and restore it after the
setup is done.

This fixes
dEQP-VK.ssbo.readonly.layout.single_struct.single_buffer.std430_instance_array_comp_access_store_cols
with address sanitizer enabled.

v2:
 - Set current block instead of disabling ldunif optimization (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12221>
 2021-08-09 13:15:24 +00:00
Marek Olšák 90ee96992c gallium/noop: implement a lot of missing context functions 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák 380898f8c6 gallium/noop: implement a lot of missing screen functions 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák c6b8591b60 gallium/noop: update pipe_screen::num_contexts 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák ddd695407e gallium/noop: enable threaded_context to test TC overhead without a driver 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák dd528305d5 gallium/noop: use threaded_transfer 
to enable threaded_context later

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák f4632f1096 gallium/noop: use threaded_resource 
to enable threaded_context later

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák 5133524a62 gallium/noop: use threaded_query 
to enable threaded_context later

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák 870a3771af gallium/noop: implement shader buffers and shader images 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák f2c04c9378 gallium/noop: implement fences 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>
 2021-08-09 12:36:27 +00:00
Marek Olšák 59fe704c45 gallium: simplify VRAM uploads by adding PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY 
When this flag is set, u_threaded_context will try not to map it directly
for better buffer placement. It's set by drivers when visible VRAM is too
small.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12257>
 2021-08-09 11:58:48 +00:00
Marek Olšák da538eb368 radeonsi: improve viewperf snx performance by forcing staging for VRAM buffers 
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12257>
 2021-08-09 11:58:48 +00:00
Samuel Pitoiset 21c8a95e34 radv: remove unnecessary FIXME about custom sample locations 
VK_EXT_sample_locations is disabled on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12247>
 2021-08-09 11:40:13 +00:00
Rhys Perry d764de6460 nir/tests: add tests for umod/imod/irem optimizations 
Both nir_opt_algebraic and nir_opt_idiv_const have optimizations for
umod/imod/irem by constants.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry e008eb1224 nir: fix signed overflow for iadd constant folding 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry b627b9fcec nir/idiv_const: optimize imod/irem 
fossil-db changes (Sienna Cichlid):
Totals from 223 (0.15% of 150170) affected shaders:
CodeSize: 384564 -> 370824 (-3.57%)
Instrs: 74518 -> 71961 (-3.43%)
Latency: 351620 -> 344640 (-1.99%)
InvThroughput: 80122 -> 74846 (-6.58%)
VClause: 919 -> 920 (+0.11%)
SClause: 2879 -> 2877 (-0.07%); split: -0.10%, +0.03%
Copies: 3099 -> 3103 (+0.13%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry 96168301f9 nir/idiv_const: improve idiv(n, INT_MIN) 
This lowering is smaller and -INT64_MIN is probably UB (signed overflow).

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry 4e2b94331b nir/algebraic: improve irem by power-of-two optimization 
Requires one less instruction.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry 2bb49e4587 nir/search: don't consider INT_MIN a negative power-of-two 
ineg(INT_MIN)/iabs(INT_MIN) won't work as expected.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry b009467b81 nir/algebraic: add optimizations for imul(a, INT_MIN) 
is_pos_power_of_two would catch this, but nir_op_imul has signed sources,
so is_neg_power_of_two catches it instead, which creates a useless
nir_op_ineg.

fossil-db (Sienna Cichlid):
Totals from 1014 (0.68% of 150170) affected shaders:
CodeSize: 3592296 -> 3592288 (-0.00%); split: -0.00%, +0.00%
Instrs: 671211 -> 670426 (-0.12%)
Latency: 5268917 -> 5268479 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 2187349 -> 2187343 (-0.00%); split: -0.00%, +0.00%
VClause: 8634 -> 8636 (+0.02%)
Copies: 97585 -> 97604 (+0.02%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry 65cd5a0f22 nir/algebraic: don't optimize umod/imod/irem if lower_bitops=true 
Match the udiv/idiv/imul by power-of-two optimizations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Rhys Perry ec4b425f59 nir/algebraic: fix imod by negative power-of-two 
If "a" is a multiple of "b", then the result would have been "b" instead
of 0.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 0ef5f3552f ("nir: add strength reduction pattern for imod/irem with pow2 divisor.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>
 2021-08-09 11:00:39 +00:00
Samuel Pitoiset 1db36422b9 radv: fix initializing the DS clear metadata value for separate aspects 
We shouldn't overwrite the clear value of the other aspect (in case
separate depth/stencil layouts are used).

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12222>
 2021-08-09 10:41:39 +00:00
Pierre-Eric Pelloux-Prayer 9fe8ae3fcd radeonsi: don't create an infinite number of variants 
If a shader has code like this:

   uniform float timestamp;
   ...
   if (timestamp > 0.0)
      do_something()

And timestamp is modified each frame, we'll end up generating a new
variant per frame.

This commit introduces a hard limit on the number of variants we generate
for a single shader.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5121
Fixes: b7501184b9 ("radeonsi: implement inlinable uniforms")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12138>
 2021-08-09 10:26:54 +00:00
Pierre-Eric Pelloux-Prayer 20055a307d radeonsi: add -t option to the test script 
This allows to easily run a subset of the tests without having
to figure out which test suite(s) they belong to.

dEQP cannot use this option because currently "deqp-runner suite"
don't have it.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12215>
 2021-08-09 10:11:58 +00:00
Pierre-Eric Pelloux-Prayer 4a69667cdd radeonsi: fix test script's output 
This line was dropped in the last refactoring. We need
to clearly state to the user if the new results are
different to the expected ones.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12215>
 2021-08-09 10:11:58 +00:00
Samuel Pitoiset ade66c1aeb radv: allow DCC MSAA fast clears if a FCE is needed 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>
 2021-08-09 09:27:52 +00:00
Samuel Pitoiset f136838d1e radv: perform a FCE for MSAA images that might have been fast-cleared 
FMASK_DECOMPRESS can't eliminate DCC fast clears. This will allow to
enable DCC MSAA fast clears that require a FCE.

Only supported on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>
 2021-08-09 09:27:52 +00:00
Samuel Pitoiset 3cfa3187cb radv: rework DCC, FMASK and FCE decompress path 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>
 2021-08-09 09:27:52 +00:00
Erik Faye-Lund 2f06642b06 gallivm: remove code to force nearest s/t interpolation 
These two bits were added in 2012, but never got wired up. Let's cut our
losses, and remove them again. 9 years unused seems sufficient.

While we're at it, remove reduction_mode from the hacks-section, because
this isn't a hack at all, rather normal state.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12240>
 2021-08-09 06:42:59 +00:00
Erik Faye-Lund 7d3ab96f39 lavapipe: lower mipmapPrecisionBits to 4 
Through some exhaustive searching, I've found that our log2 approximation
is precise to around 3.5 bits. And the squaring step should increase the
result with one bit, leaving us with 4.5 bits of precision.

Reporting the right mipmap precision fixes a few CTS-tests.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12238>
 2021-08-09 06:27:10 +00:00
Tapani Pälli 5e80cdbf8e anv: allow stencil memory export 
This commit reverts 58e9371141 as now iris driver can import stencil.
This makes ext_external_objects-vk-stencil-display pass and X-Plane 11
vulkan rendering backend to work with anv + iris.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>
 2021-08-09 05:38:50 +03:00
Tapani Pälli e08370dc37 anv: disable aux for exportable images without modifiers 
This makes import easier on different gfx generations and we don't
have to lock down on a certain aux layout just yet.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>
 2021-08-09 05:38:50 +03:00
Tapani Pälli d75502be33 iris: handle depth-stencil import with a wrapper function 
This is similar to u_transfer_helper wrap but implemented in
the driver as the layout between drivers can vary.

v2: remove else, simplify (Rohan, Eleni)
v3: add hiz surface support when importing depth buffer
v4: use iris_resource_configure_aux_offsets for setting
    aux offsets for depth
v5: introduce helper for configuring imported memobj aux
    offsets and utilize that
v6: simplify, remove aux support for now
v7: cleanups, fix offset calculation (Nanley)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>
 2021-08-09 05:38:50 +03:00
Tapani Pälli 5f7df5df0d crocus: disable depth and d+s formats with memory objects 
This is similar to i965 commit ba11f673a2, we set depth and
d+s formats unsupported for now.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>
 2021-08-09 05:38:50 +03:00
Tapani Pälli e47b72e931 crocus: take a reference to memobj bo in crocus_resource_from_memobj 
This is the same fix as commit 2d87ea3166 for iris driver.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>
 2021-08-09 05:38:50 +03:00
Emma Anholt 13677a9092 i915g: Reapply clang-format. 
Missed this in 2008ec8a43 ("i915g: Fix writemasking of SEQ/SNE/SSG.")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12250>
 2021-08-09 04:40:21 +00:00
Emma Anholt 01e9824997 i915g: Use the devmaster quadratic approximation for sin/cos. 
11 instructions, but now processes up to 4 channels at once (since TGSI
splits to scalar for these math ops) while being higher accuracy.
Previously we used 6 instructions per channel, but it didn't look like a
sine wave.  i915c managed it in 9 instructions per scalar channel, thanks
to avoiding an extra mov we do for the fabs (should be fixable), and
avoiding an extra MUL (maybe just needs reassociation of our immediates?).
But, the ALU count win from doing 4 channels at once will be way more
important for making sure that programs compile than those 2 ALU ops, plus
now we do it in NIR instead of assembly.

Closes: #4981
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12250>
 2021-08-09 04:40:21 +00:00
Dmitry Baryshkov f800b9182b freedreno/regs: add bit to control continuous clock with 7nm PHYs 
7nm PHYs need another special bit set in DSI_LANE_CTRL to enable
continuous DSI clock. Document this bit.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11219>
 2021-08-08 20:15:42 +00:00
Filip Gawin fd9310f885 docs: make most important part of bugs.rst easier to find 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12124>
 2021-08-08 19:53:15 +00:00