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Author SHA1 Message Date
Rhys Perry dc01f03d1b radv: remove is_internal pipeline creation parameter 
Instead, check if the cache is the meta shader cache. This catches the
shaders created by radv_create_radix_sort_u64().

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21606>
 2023-03-02 16:48:09 +00:00
Karmjit Mahil 9905322df9 pvr: Advertise STORAGE_IMAGE_BIT for B10G11R11_UFLOAT_PACK32 
For optimalTilingFeatures we should be advertising
STORAGE_IMAGE_BIT for B10G11R11_UFLOAT_PACK32 too.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21649>
 2023-03-02 16:33:53 +00:00
Karmjit Mahil 225ae96357 pvr: Don't advertise currently unsupported features 
This commit removes the advertising of features that are currently
unsupported by the driver and aren't strictly necessary for
Vulkan 1.0.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21649>
 2023-03-02 16:33:53 +00:00
Samuel Pitoiset 4ec6850210 radv: fix DCC decompress on GFX11 
The hardware requires one color output to be set by CB registers,
otherwise the DCC decompression does nothing.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8127
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8175
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8370
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21629>
 2023-03-02 16:03:31 +00:00
Tatsuyuki Ishi 57ab623f0b radv: Use common helpers to translate format in SDMA copy. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21585>
 2023-03-02 15:29:47 +00:00
Tatsuyuki Ishi 4f681d5e2c radv: Remove SDMA padding from copy helpers. 
These are handled in winsys already; no need to duplicate and complicate
the code paths.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21585>
 2023-03-02 15:29:47 +00:00
Tatsuyuki Ishi e9a55b332a radv: SDMA v4 size field is size - 1 
After cross-checking with kernel and the old buffer copy code, it seems
that the size field should be size - 1 instead.

Fixes: 7b5ab48c40 ("radv: partial sdma support")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21585>
 2023-03-02 15:29:47 +00:00
Tatsuyuki Ishi 4f50497a96 radeonsi: SDMA v4 size field is size - 1 
After cross-checking with kernel and the old buffer copy code, it seems
that the size field should be size - 1 instead.

Fixes: 46c95047bd ("radeonsi: implement si_sdma_copy_image for gfx7+")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21585>
 2023-03-02 15:29:47 +00:00
Lionel Landwerlin c914e70bce anv/hasvk: speed up null image/view descriptor writes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21642>
 2023-03-02 15:03:25 +00:00
Kai-Heng Feng 646cff13bc Revert "iris: Avoid abort() if kernel can't allocate memory" 
This reverts commit f9d8d9acbb.

Now ENOMEM is handled in submit_batch(), we don't need to check it for
resetting anymore.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20449>
 2023-03-02 14:30:17 +00:00
Kai-Heng Feng 5aae8a0526 iris: Retry DRM_IOCTL_I915_GEM_EXECBUFFER2 on ENOMEM 
We are seeing endless DRM_IOCTL_SYNCOBJ_WAIT ioctl when system memory is
under pressured.

Commit f9d8d9acbb ("iris: Avoid abort() if kernel can't allocate
memory") avoids the abort() on ENOMEM by resetting the batch. However,
when there's an ongoing OpenGL query, resetting the batch will make the
snapshots_landed never be flipped, so iris_get_query_result() gets stuck
in the while loop forever.

Since there's no guarantee that the next batch after resetting won't hit
ENOMEM, so instead of resetting the batch, be patient and wait until kernel has
enough memory. Once the batch is submiited and snapshots_landed gets
flipped, iris_get_query_result() can proceed normally.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6851
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20449>
 2023-03-02 14:30:17 +00:00
Tapani Pälli 207eb94445 intel/compiler: add comment about workaround on simd width 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21619>
 2023-03-02 14:06:36 +00:00
Samuel Pitoiset 427fd83d27 radv: use new EVENT_WRITE_ZPASS packet3 on GFX11 
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21621>
 2023-03-02 12:53:27 +00:00
Samuel Pitoiset 87444bb7ab radv: ignore alpha_is_on_msb on GFX11 because the hw ignores it 
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21621>
 2023-03-02 12:53:27 +00:00
Georg Lehmann 0a3387a190 nir/lower_mediump: don't use fp16 for constants if the result is denormal 
Image stores are not required to preserve denorms.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21622>
 2023-03-02 11:42:10 +00:00
Georg Lehmann ede0630f9e aco: use v_fma_mix_f32 for v_fma_f32 with 2 fp16 representable, different literals 
We can pack two fp16 literals into one 32bit literal and use opsel to select
the correct value. Note that LLVM currently disassembles these instructions
incorrectly.

Foz-DB Navi21:
Totals from 13365 (9.91% of 134913) affected shaders:
VGPRs: 840880 -> 840016 (-0.10%); split: -0.11%, +0.01%
SpillSGPRs: 724 -> 722 (-0.28%)
CodeSize: 82439364 -> 82451336 (+0.01%); split: -0.06%, +0.08%
MaxWaves: 244858 -> 244980 (+0.05%)
Instrs: 15265976 -> 15247201 (-0.12%); split: -0.13%, +0.01%
Latency: 223316180 -> 223272495 (-0.02%); split: -0.03%, +0.02%
InvThroughput: 41981375 -> 41969917 (-0.03%); split: -0.04%, +0.01%
VClause: 266775 -> 266558 (-0.08%); split: -0.14%, +0.06%
SClause: 646602 -> 645996 (-0.09%); split: -0.16%, +0.07%
Copies: 794703 -> 776075 (-2.34%); split: -2.46%, +0.12%
Branches: 296317 -> 296316 (-0.00%)
PreSGPRs: 658796 -> 656479 (-0.35%); split: -0.35%, +0.00%
PreVGPRs: 744014 -> 743679 (-0.05%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20587>
 2023-03-02 10:59:05 +00:00
Georg Lehmann ed349951cb aco: mark mad definition as precise if the mul/add were precise 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20587>
 2023-03-02 10:59:05 +00:00
Samuel Pitoiset f19fccd9f8 amd,ac/rgp: fix SQTT memory types 
This crashed on Steam Deck because the memory type is LPDDR5 and it
wasn't not handled in the switch. It seems the kernel changed the
memory type returned for VanGogh because it used to work.

Fixes: aef7ea868f ("ac/gpu_info: handle LPDDR4 and 5 in ac_memory_ops_per_clock")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21627>
 2023-03-02 07:54:35 +00:00
Emma Anholt bb122202b6 gallivm: Add some notes about other invocation_0_must_be_active usages. 
So that the next person trying to cut down LLVM compile times doesn't trip
over this.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>
 2023-03-02 04:47:35 +00:00
Emma Anholt 66dff3d39c gallivm: Use first_active_invocation for scalar SSBO loads. 
Again, this should reduce the complexity of the LLVM IR we emit in some
cases.  We don't use it for shared loads, due to the noted corner case.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>
 2023-03-02 04:47:35 +00:00
Emma Anholt a2b054c8f0 gallivm: Use first_active_invocation for ubo/kernel memory loads. 
If we're just loading memory, we can take the scalar offset_is_uniform
paths even the first active invocation is nonzero, saving a bunch of
looping and bounds checking for per-element loads.  And, if we don't have
an active invocation, doing the load for element 0 (which is
bounds-checked to return 0 if element 0 had a bad value in it) before
throwing away the result is still better than doing bounds-checked loads
for each element before throwing away the result.

dEQP-VK.ubo.random.16bit.scalar.92 goes from 16.5 to 14.0 seconds.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>
 2023-03-02 04:47:35 +00:00
Emma Anholt 1be626b618 gallivm: Return 0 for first active invocation when no invocations are active. 
gallivm doesn't actuially jump across branches where no invocations are
active, so my previous assertion about the exec mask being nonzero was
incorrect.  This means that we'll always use a defined invocation for the
various LLVMBuildExtractElements using the result value, which is an
improvement over my even the code before my cttz change that would use
undefined values for the element to be extracted.

Fixes: 8c2493d041 ("gallivm: Use cttz instead of a loop for first_active_invocation().")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21142>
 2023-03-02 04:47:35 +00:00
Chia-I Wu e2c67ed63e ci/radv: remove dEQP-VK.image.sample_texture.* fails/flakes 
They were fixed since commit 11b2a063bf ("vulkan: Unconditionally add
barriers for missing external subpass deps").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21616>
 2023-03-02 00:56:16 +00:00
Mark Janes 3c9a8f7a6d intel/dev: generate helpers to identify platform workarounds 
Workarounds for defects in Intel silicon have been manually
implemented:

 - consult defect database for the current platform

 - add workaround code behind platform ifdef or devinfo->ver checks

Some bugs have occurred due to the manual process.  Typical failure
modes:

 - defect database is updated after a platform is enabled

 - version checks are overly broad (eg gfx11+) for defects that were
   fixed (eg in gfx12)

 - version checks are too narrow for defects that were extended to
   subsequent platforms.

 - missed workarounds

This commit automates workaround handling:

 - Internal automation queries the defect database to collate and
   summarize defect documentation in json.

 - mesa_defs.json describes all public defects and impacted platforms.
   Defects which are extended to subsequent platforms are listed under
   the original defect.

 - gen_wa_helpers.py generates workaround helpers to be called
   in place of version checks:

   - NEEDS_WORKAROUND_{ID} provides a compile time check suitable for
     use in genX routines.

   - intel_device_info_needs_wa() provides a more precise runtime
     check, differentiating platforms within a generation and
     platform steppings.

Internal automation will generate new mesa_defs.json as needed.
Workarounds enabled with these helpers will apply correctly based on
updated information in Intel's defect database.

Reviewed-by: Dylan Baker <dylan@pnwbakers>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Mark Janes f11aab743b util: add macro to support gcc/clang poison 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Dylan Baker a0fa31bcdd intel/dev: create a helper dependency for libintel_dev 
This ensures that users of libintel_dev.a won't be compiled until
include files are generated, and that they are recompiled when the
header changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Marek Olšák 98198a7782 glthread: fix a perf regression due to draw_always_async flag, fix DrawIndirect 
Performance regressed by 31% in one VP2020/Creo subtest because
the draw_always_async flag wasn't implemented correctly. Remove it
instead of fixing it.

While removing it, I noticed that our DrawIndirect async conditions
were incorrect. I fixed them.

Fixes: 3b897719e6 - glthread: add ctx->GLThread.draw_always_async to simplify draw checking

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21566>
 2023-03-01 23:18:10 +00:00
Illia Polishchuk 1eab7e69e2 glx: fix indirect initialization crash 
Fixes: b090246a ("glx: Only compute client GL extensions for indirect contexts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8393

Reviewed-by: Adam Jackson <ajax@redhat.com>

Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21591>
 2023-03-01 19:54:00 +00:00
Giancarlo Devich cc3c8c241e d3d12: Use memcmp for full tcs/gs variant keys 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>
 2023-03-01 19:40:06 +00:00
Giancarlo Devich f53188b7fa d3d12: Cache varying info to reduce compare/copy cost 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>
 2023-03-01 19:40:06 +00:00
Giancarlo Devich e4ba343ac9 d3d12: Compare shader key common parts with memcmp, instead of if's 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>
 2023-03-01 19:40:06 +00:00
Giancarlo Devich 623a01827c d3d12: Compare shader keys with union-encompassing fields all at once 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>
 2023-03-01 19:40:06 +00:00
Giancarlo Devich ebd925e79c d3d12: Compare shader keys with a switch, instead of cascading if's 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21610>
 2023-03-01 19:40:06 +00:00
Iván Briano 4887b88d22 anv: use the parameter passed to the macro 
The two points calling this macro pass dyn->rs.provoking_vertex to it,
which is why it works, but it's cleaner to use the parameter instead.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21613>
 2023-03-01 19:07:41 +00:00
Dylan Baker a8691f916b intel/mi: use 64bit constant for bitshift 
Coverity complains that we could end up rolling over on a 32bit
platform, which isn't really true because of the assertion, but there's
also no harm in ensuring that we have exactly the same behavior for both
32 bit and 64 bit platforms.

CID: 1515989
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21572>
 2023-03-01 18:42:25 +00:00
Yiwei Zhang 054a83492d venus: fix VK_EXT_image_view_min_lod feature query 
Fixes: 8b81098519 ("venus: enable VK_EXT_image_view_min_lod")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21617>
 2023-03-01 17:24:26 +00:00
Karmjit Mahil 1dfd535124 pvr: Setup SPM background object 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21575>
 2023-03-01 17:10:53 +00:00
Timothy Arceri d75a36a9ee glsl: remove do_copy_propagation_elements() optimisation pass 
Since 13b859de do_copy_propagation_elements() has a flaw where
the time it takes to complete grows exponentially slowers as the number
of nested loops increases. It can also hurt rather than help verses
just letting NIR optimise the code. So if the NIR linker is enabled we
let it handle it instead.

shader-db results Iris (BDW):

total instructions in shared programs: 11177181 -> 11199739 (0.20%)
instructions in affected programs: 119424 -> 141982 (18.89%)
helped: 109
HURT: 65
total cycles in shared programs: 368946819 -> 372277173 (0.90%)
cycles in affected programs: 116539428 -> 119869782 (2.86%)

total spills in shared programs: 3983 -> 8785 (120.56%)
spills in affected programs: 2072 -> 6874 (231.76%)
helped: 0
HURT: 6

total fills in shared programs: 2016 -> 6068 (200.99%)
fills in affected programs: 230 -> 4282 (1761.74%)
helped: 0
HURT: 6

LOST:   85
GAINED: 77

freedreno results:

total instructions in shared programs: 11011122 -> 11011620 (<.01%)
instructions in affected programs: 939829 -> 940327 (0.05%)
total full in shared programs: 762725 -> 762674 (<.01%)
full in affected programs: 1096 -> 1045 (-4.65%)
total constlen in shared programs: 1772092 -> 1771596 (-0.03%)
constlen in affected programs: 2780 -> 2284 (-17.84%)
total stp in shared programs: 4040 -> 4058 (0.45%)
stp in affected programs: 3656 -> 3674 (0.49%)
total ldp in shared programs: 2160 -> 2178 (0.83%)
ldp in affected programs: 1748 -> 1766 (1.03%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/13.shader_test CL: 1231 -> 1234 (0.24%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/13.shader_test CL: 1231 -> 1234 (0.24%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/15.shader_test CL: 453 -> 456 (0.66%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/15.shader_test CL: 453 -> 456 (0.66%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/17.shader_test CL: 144 -> 147 (2.08%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/17.shader_test CL: 144 -> 147 (2.08%)

however, those stp counts are misleading -- gfxbench gl-5-normal actually
gets its scratch (ldp/stp) stored as 16 bits instead of 32 thanks to
better NIR copy prop, and the result is 2.64398% +/- 0.0991923% perf
improvement!

i915 results:

total instructions in shared programs: 510528 -> 510489 (<.01%)
instructions in affected programs: 3303 -> 3264 (-1.18%)
total tex_indirect in shared programs: 16708 -> 16717 (0.05%)
tex_indirect in affected programs: 134 -> 143 (6.72%)
total temps in shared programs: 30181 -> 30169 (-0.04%)
temps in affected programs: 1268 -> 1256 (-0.95%)
LOST:   0
GAINED: 1

i915 highlights:
instructions HURT:   shaders/closed/steam/legend-of-grimrock/47.shader_test FS: 141 -> 144 (2.13%)
instructions HURT:   shaders/closed/steam/steamworld-dig/22.shader_test FS: 84 -> 108 (28.57%)
temps HURT:   shaders/closed/steam/left-4-dead-2/medium/3682.shader_test FS: 7 -> 13 (85.71%)

r300 results:

total instructions in shared programs: 1340439 -> 1340845 (0.03%)
instructions in affected programs: 32354 -> 32760 (1.25%)
total temps in shared programs: 179394 -> 179329 (-0.04%)
temps in affected programs: 1505 -> 1440 (-4.32%)
total consts in shared programs: 1177742 -> 1177885 (0.01%)
consts in affected programs: 1107 -> 1250 (12.92%)
total lits in shared programs: 24992 -> 25019 (0.11%)
lits in affected programs: 138 -> 165 (19.57%)
instructions HURT:   shaders/closed/steam/legend-of-grimrock/26.shader_test FS: 47 -> 52 (10.64%)
instructions HURT:   shaders/closed/steam/sanctum-2/6072.shader_test FS: 43 -> 48 (11.63%)
instructions HURT:   shaders/closed/steam/champions-of-regnum/2378.shader_test VS: 35 -> 40 (14.29%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13288>
 2023-03-01 16:09:25 +00:00
Emma Anholt 106019a5d8 nir/split_64bit_vec3_and_vec4: Handle 64-bit matrix types. 
The offset handling should already work for flattening to our split vars,
just need to make sure we have enough (or any!) array elements.

Fixes: #7154
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13288>
 2023-03-01 16:09:25 +00:00
Caio Oliveira 5f79e78911 spirv: Add skip_os_break_in_debug_build option to use in unit tests 
When running in the CI environment, instead of crashing the test
binary, it is preferable to just fail gracefully (in this case return
a NULL shader) like is done in release mode, so other tests continue
to be executed.

For convenience add a variable break_on_failure to the test so the
breaking behavior can be re-enable in individual tests when debugging.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>
 2023-03-01 13:47:57 +00:00
Caio Oliveira 8a91a33b7c spirv/tests: Add some basic control flow tests 
The DISABLED test currently fails parsing.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>
 2023-03-01 13:47:57 +00:00
Caio Oliveira 4e5b520286 spirv/tests: Parametrize stage in get_nir() helper 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>
 2023-03-01 13:47:57 +00:00
Caio Oliveira 131f328a18 spirv/tests: Add script to generate C array from SPIR-V source 
This is useful for generating the C code to embed the SPIR-V
when adding a new test.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>
 2023-03-01 13:47:57 +00:00
Caio Oliveira 17e0c75441 spirv/tests: Subclass spirv_test helper to namespace the tests 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21512>
 2023-03-01 13:47:57 +00:00
David Heidelberg 4cc0cec473 ci: implement unified sections 
in after_script, variable $SCRIPTS_DIR is lost

Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20272>
 2023-03-01 12:02:24 +00:00
David Heidelberg 5bfc17b2da ci: alpine: install bash and coreutils for date -d 
bash is needed for consistency.
coreutils is needed for `date -d`.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20272>
 2023-03-01 12:02:24 +00:00
David Heidelberg 6f0fcb0a0c ci/alpine: keep the curl inside the image 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20272>
 2023-03-01 12:02:24 +00:00
Georg Lehmann aeb68c29b4 nir/opt_algebraic: add patterns for iand/ior of feq/fneu with 0 
Foz-DB Navi21:
Totals from 1245 (0.92% of 134913) affected shaders:
VGPRs: 66232 -> 66248 (+0.02%); split: -0.01%, +0.04%
CodeSize: 5874976 -> 5868168 (-0.12%); split: -0.17%, +0.05%
MaxWaves: 25278 -> 25274 (-0.02%); split: +0.01%, -0.02%
Instrs: 1087502 -> 1085267 (-0.21%); split: -0.21%, +0.00%
Latency: 6531489 -> 6531672 (+0.00%); split: -0.04%, +0.05%
InvThroughput: 1531774 -> 1532327 (+0.04%); split: -0.02%, +0.05%
VClause: 22218 -> 22202 (-0.07%); split: -0.08%, +0.00%
SClause: 45906 -> 45873 (-0.07%); split: -0.08%, +0.01%
Copies: 64004 -> 64102 (+0.15%); split: -0.24%, +0.39%
Branches: 21529 -> 21534 (+0.02%); split: -0.00%, +0.03%
PreSGPRs: 51936 -> 51850 (-0.17%)
PreVGPRs: 55393 -> 55398 (+0.01%); split: -0.02%, +0.03%

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21576>
 2023-03-01 11:24:43 +00:00
Samuel Pitoiset 3ced4ae816 radv: only expose EXT_pipeline_library_group_handles if RT is enabled 
VK_EXT_pipeline_library_group_handles requires
VK_KHR_ray_tracing_pipeline to be enabled.

Fixes dEQP-VK.info.device_extensions.

Fixes: ed76833705 ("radv: Implement & expose VK_EXT_pipeline_library_group_handles.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21618>
 2023-03-01 10:55:00 +00:00
Caio Oliveira 863cbb3e02 spirv: Don't specify nir_var_uniform or nir_var_mem_ubo in barriers 
These are constant read-only data and don't need to be synchronized.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21517>
 2023-03-01 09:53:29 +00:00