Commit Graph

8222 Commits

Author SHA1 Message Date
Tomeu Vizoso
477412f303 iris/ci: Set FDO_CI_CONCURRENT for all Chromebook jobs
For some reason we were missing these and that was causing some CPUs to
remain idle, and some boards to have too high load and some tests timing
out occasionally.

Set FDO_CI_CONCURRENT for the number of cores, plus one to account for
GPU and I/O waits.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18028>
2022-08-15 11:40:16 +02:00
Tomeu Vizoso
1bdcf5c099 iris/ci: Test on Jasper Lake Chromebooks
8 such boards have been added to Collabora's lab, let's run all tests
from the selected set.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18028>
2022-08-15 11:40:12 +02:00
Yonggang Luo
44a64a34bf intel: Fixes compile error of aubinator_viewer.cpp with gcc
Remove '-Wno-class-memaccess' from cpp_args because clang don't support this option

aubinator_viewer.cpp:1183:39: error: 'void* memset(void*, int, size_t)' clearing an object of non-trivial type 'struct Context'; use assignment or value-initialization instead [-Werror=class-memaccess]
 1183 |    memset(&context, 0, sizeof(context));

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18024>
2022-08-12 18:06:36 +00:00
Konstantin Kharlamov
91362340f3 meson: remove source_root() call in nir compiler path
source_root function is deprecated in Meson version 0.56.0, so let's use
instead a current_source_dir() function, available in all Meson
versions. This also allows to deduplicate some code by declaring
commonly used string at the top meson.build file.

Signed-off-by: Konstantin Kharlamov <Hi-Angel@yandex.ru>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17974>
2022-08-12 13:11:03 +00:00
sjfricke
861167f41d isl: fix bug where sb.MOCS is not being set
Currently the sb.MOCS is being reset to zero after struct init.

Signed-off-by: sjfricke <spencerfricke@gmail.com>
Fixes: c27fcb1d3b ("isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17985>
2022-08-12 12:35:54 +00:00
Lionel Landwerlin
00d8fcee10 intel/drm-shim: update shim to support DG2
We were missing :
  * GEM_CREATE_EXT (for local memory allocations)
  * MMAP_OFFSET (new version of mmap required on DG2)
  * GEOMETRY_SUBSLICE query (also required on DG2)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18005>
2022-08-11 22:45:07 +03:00
Lionel Landwerlin
56bb29cb93 anv: don't return incorrect error code for vkCreateDescriptorPool
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7013
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17945>
2022-08-11 14:29:33 +00:00
Pierre-Eric Pelloux-Prayer
70891edd97 nir: add a nir_opt_if_options enum
And don't enable nir_opt_if_optimize_phi_true_false on radeonsi with
LLVM 14 because it crashes Blender.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6976
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17949>
2022-08-10 12:55:39 +00:00
Iván Briano
fbd4133735 anv: emit scissors when the pipeline changes
With the switch to common dynamic state tracking, something got lost
that made the scissors not always be emitted when they are not dynamic
and the pipeline is marked dirty.

Since both viewport and scissors make use of each other to calculate
their values, just stick the scissor emit in the same if block as
viewport for now.
I'd rather have them decoupled, and at least the Vulkan CTS didn't
complain when I tried it, but I don't know what other effects that
may have, especially when it comes to the guardband.

Fixes a bunch of tests under
dEQP-VK.pipeline.*.multisample.misc.*

Fixes: 7d25c04236 ("anv: Switch to using common dynamic state tracking")

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17964>
2022-08-09 19:58:14 +00:00
Timothy Arceri
8bffd601ed Revert "nir: Preserve offsets in lower_io_to_scalar_early"
This reverts commit 96fa23bca5.

The correct fix to the problem was a1bc152340, making this
change obsolete as the pass skips any vars marked with
always_active_io. There was no real advantage to allowing these
vars to be split because they can't be removed anyway. Also there
is no way to split varying arrays gracefully here due to the xfb
layout rules, and this change didn't handle arrays at all.

Removing this obsolete code also fixes an assert in the new CTS
test KHR-Single-GL45.enhanced_layouts.xfb_all_stages. The test
was legally adding xfb offsets to all vertex stages but since
we only mark the varyings in the final vertex stage with the
always_active_io flag the other stages were correctly lowering
to scalars but when an array with an offset hit this code it
asserted since it couldn't handle it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

Fixes: a1bc152340 ("spirv: mark variables decorated with XfbBuffer as always active")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6928
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17878>
2022-08-08 01:37:20 +00:00
Emma Anholt
cbbd9f3402 ci: Upgrade deqp-runner to 0.15.0.
This includes the new timeout fixes so that tests that throw lots of debug
don't delay the timeout triggering, and the fraction vs shuffling behavior
change so that "--fraction 2" doesn't just skip every other test as it
appears in the caselist (every vertex shader variant, for example).

The fraction vs shuffling change does mean we see some different fails on
some drivers now.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17876>
2022-08-07 02:11:46 +00:00
Emma Anholt
f01ae0203d ci: Add testing of the khr-single tests.
These got split out from gl4[3456]-master a while back, so we were missing
coverage in CI.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17876>
2022-08-07 02:11:46 +00:00
Jason Ekstrand
239623ecee anv: Don't require 32-bit addresses for scratch on Gen12.5+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Jason Ekstrand
d82cea5fc3 genxml: Add BVH data structures
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Jason Ekstrand
a680083546 intel/rt: Handle multiple exits in lower_shader_returns
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Jason Ekstrand
a329e6e511 intel/rt: Handle halts in any-hit shaders properly
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Jason Ekstrand
caed8df146 intel/fs_reg_allocate: Improve compressed instruction self-interference
The old version worked fine for SIMD16 instructions but SIMD8
instructions where the destination spans two registers have the same
problem.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Lionel Landwerlin
1ce5be916f intel/nir: specify synchronous value for tracing op
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Lionel Landwerlin
03ab1d6aaa intel/compiler: document units of brw_ubo_range fields
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Lionel Landwerlin
734384e8bc intel/fs: fixup simd selection with shader calls
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Lionel Landwerlin
9cb9390962 intel/fs: store num of resume shaders in prog_data
That way we can look at the SBT entries for debug purposes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
2022-08-05 11:51:31 +00:00
Sagar Ghuge
845ab3d627 anv: Handle bits to flush data-port's Untyped L1 data cache
v2: Drop ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT from invalidate bits (Lionel)
    Add utrace support
    Expand on comment about PIPE_CONTROL::UntypedDataPortCache

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
2022-08-05 10:43:50 +03:00
Lionel Landwerlin
1f34ce7e8e intel/ds: track untyped dataport flushes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
2022-08-05 10:43:50 +03:00
Sagar Ghuge
79cd2c2759 anv: Specify Untyped L1 cache policy for stateless accesses
Set write back L1 cache policy in STATE_BASE_ADDRESS instruction for A64
messages.

v2: Also set the value in genX_state.c (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
2022-08-05 10:43:50 +03:00
Sagar Ghuge
d4b2b769d1 intel/isl: Setting L1 caching policy to Write-back mode
For a RW L1 cache, both reads and writes are cached in the L1, at high
priority (MRU position). For a RO L1 cache, reads are cached at higher
priority and writes bypass the cache.

v1: (Ken)
- Set caching policy for buffer surfaces too

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
2022-08-05 10:43:50 +03:00
Lionel Landwerlin
5e21f47428 anv: fixup PIPE_CONTROL restriction on gfx8
We're missing a condition that is currently papered over by having
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT in the invalidate bits.

v2: rework with simplication (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
2022-08-05 10:42:16 +03:00
Dave Airlie
a17635e988 gallivm/nir/st: lower image derefs in advance.
This improves clover from crashing to just failing, but I mainly
want it this to cleanup the nir code first

It's also important the shaders coming from the state tracker
for feedback get images lowered when they are draw shaders now.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10641>
2022-08-05 06:18:44 +00:00
Constantine Shablya
2af624706a anv: use nir_opt_uniform_access
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17558>
2022-08-03 23:57:50 +00:00
Nanley Chery
e7419c11ae anv: Make the D16 reg mode single-sampled
Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.

As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.

Make the workaround tracking code sample-dependent to fix this.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
2022-08-03 15:31:10 +00:00
Mykhailo Skorokhodov
8b13acd715 anv: Move Wa_1806527549 and enable by default
Move Wa_1806527549 into `init_render_queue_state` and
set HIZ_CHICKEN (7018h) bit = 1 by default.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6717
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17778>
2022-08-02 16:33:10 +03:00
Lionel Landwerlin
8c9dd9e783 intel/dev: remove INTEL_DEVID_OVERRIDE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
2022-08-02 11:17:58 +00:00
Lionel Landwerlin
7f82ab7104 intel/dev: add a test verifying that device override works
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
2022-08-02 11:17:58 +00:00
Lionel Landwerlin
9d55c5237e intel/tools/stub: fixup parsing of --platform=
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
2022-08-02 11:17:58 +00:00
Lionel Landwerlin
f2bbc959a0 intel/tools/drm-shim: fixup eu_stride for topology
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
2022-08-02 11:17:58 +00:00
Lionel Landwerlin
186ff4696a intel/dev: move verification function to a header
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17831>
2022-08-02 11:17:58 +00:00
Lionel Landwerlin
6931ae83ce anv: decode init batch with INTEL_DEBUG=bat
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17852>
2022-08-02 10:42:26 +00:00
Marcin Ślusarz
883acc4150 intel/compiler: use NIR_PASS more
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17619>
2022-08-02 10:07:05 +00:00
Marcin Ślusarz
7ebae85955 intel/compiler: insert URB fence before task/mesh termination
Bspec 53421 says:
"A URB fence memory is typically performed prior the thread
exit message, so that the next thread dispatch that reads
that URB memory will see it."

Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16665>
2022-08-02 09:31:24 +00:00
Marcin Ślusarz
30c0f2bfbb intel/compiler: there are 4 types of fences on gfx >= 12.5
Found by code inspection.

There's an assert later checking that we haven't overflown
this array, so this change probably doesn't matter for any
workload.

Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16665>
2022-08-02 09:31:24 +00:00
Marcin Ślusarz
2bd148c990 intel/compiler: emit URB fences for TASK/MESH
Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16665>
2022-08-02 09:31:24 +00:00
Kenneth Graunke
9afd955353 intel/compiler: Delete unused Gfx8+ code in brw_find_live_channel()
We now handle this in fs_visitor::lower_find_live_channel().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17530>
2022-08-02 08:41:43 +00:00
Kenneth Graunke
49ee3ae9e8 intel/compiler: Lower FIND_[LAST_]LIVE_CHANNEL in IR on Gfx8+
This allows the software scoreboarding pass, scheduler, and so on
to handle the individual instructions and handle them, rather than
trusting in the generator to do scoreboarding correctly when expanding
the virtual instruction to multiple actual instructions.

By using SHADER_OPCODE_READ_SR_REG, we also correctly handle the
software scoreboarding workaround when reading DMask/VMask.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17530>
2022-08-02 08:41:43 +00:00
Mark Janes
6401d768b9 intel/dev: drop warning for unhandled hwconfig keys
The hwconfig api may change unexpectedly prior to public release of
new platforms.  Also, public documentation of the hwconfig api
sometimes lags the release.

For these reasons, warnings about unhandled hwconfig keys are noisy,
likely to occur, and unhelpful to most users.  This commit drops those
warnings, in favor of a separate internal process for tracking
hwconfig api changes.

Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by:  Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17846>
2022-08-02 08:08:02 +00:00
Jordan Justen
68b88fae8c intel/dev: Fill in system memory info when using INTEL_DEVID_OVERRIDE
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17828>
2022-08-01 23:54:55 +00:00
Sviatoslav Peleshko
cb99365403 intel/nullhw: Use correct macro to fix build regression
Fixes: b510ee0d ("Use vk_foreach_struct_const where needed")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6950

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17789>
2022-08-01 10:54:38 +00:00
Yiwei Zhang
71a0ae2796 anv: enable VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM for modifier support
This is a missed format to properly support media interop for Android.
Currently only used when layering GL atop Vulkan on Android, but will
be used directly with Vulkan when the platform default renderer has
switched to skiavk in modern Android.

Test: CtsMediaTestCases and CtsVideoTestCases with angle on venus on anv

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17808>
2022-07-29 23:24:15 +00:00
Iván Briano
a05fcc94c2 anv: assert inheritance_info is not NULL
Makes some static analysis tools happier.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17809>
2022-07-29 22:50:21 +00:00
Mark Janes
dc8df485e9 intel/compiler: reorder shader cache keys to minimize padding
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17749>
2022-07-29 20:45:25 +00:00
Mark Janes
a4a4aefa03 intel/compiler: pad all data structures used by shader cache keys
When the compiler pads a data structure, the padded bytes will not be
initialized.  Shader keys are compared with memcmp and unitialized
bytes within the structure breaks this mechanism.

Explicitly pad the structures with members, so the compiler is forced
to initialize them.  Add a warning to indicate if a change to
alignment in any of the data structures requires additional padding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17749>
2022-07-29 20:45:25 +00:00
Dylan Baker
42b89276e6 iris|anv: gfx version 12.5 data cache flush is not a workaround
This was not a workaround, it was simply missing from the documentation.
So remove the workaround language.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17797>
2022-07-28 22:08:46 +00:00