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Author SHA1 Message Date
Daniel Schürmann d34d2f8fa8 nir: consider loop invariance in nir_src_is_divergent() 
By doing so, this function does not require LCSSA form anymore
in order to provide correct results.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 1a55d6c23b nir/divergence: Introduce and set nir_def::loop_invariant 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c0b3d7a916 nir/divergence: require nir_metadata_block_index 
This allows for fast checks whether some value is defined inside a loop.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 8d1abd4996 treewide: use nir_src_is_divergent() rather than checking the divergence of the SSA 
Without LCSSA, divergence between src and def might differ.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c8348139fd nir: change signature of nir_src_is_divergent() 
Now, it takes nir_src * instead of nir_src.
Also move the implementation to nir_divergence_analysis.c.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 421b42637d nir: remove nir_update_instr_divergence() 
This function has obscure limitations.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann ce0a3fe645 nir/opt_uniform_atomics: don't preserve divergence information 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c25c63ebc0 nir/divergence: separately indicate whether loops have divergent continues or breaks 
bool nir_loop_is_divergent(nir_loop *)
 replaces the previous loop->divergent indicator.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Jordan Justen a4c5bfd34c intel/dev: Use hwconfig for urb min/max entry values 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen 7b86da0ccd intel/dev: Allow specifying a version when to always use hwconfig 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen a71702d342 intel/dev: Simplify DEVINFO_HWCONFIG_KV by adding should_apply_hwconfig_item() 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen b4df9658f5 intel/dev: Rework DEVINFO_HWCONFIG; add DEVINFO_HWCONFIG_KV macro 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Vignesh Raman ce98715566 ci/crosvm: Use default value for CROSVM_GALLIUM_DRIVER 
Use a default value for CROSVM_GALLIUM_DRIVER. This change
ensures that if the variable is unset, it defaults to an
empty string. This prevents unbound variable errors with
set -u in the case of drm-ci.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31814>
 2024-10-24 08:46:54 +00:00
Stéphane Cerveau ac2b7d07e4 anv: check that inline query pool is VK_NULL_HANDLE 
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Stéphane Cerveau <scerveau@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31765>
 2024-10-24 08:17:11 +00:00
Stéphane Cerveau aaa5770d4b anv: inline query for vulkan video encode 
Follow up of the work performed in decode to
support inline query.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Signed-off-by: Stéphane Cerveau <scerveau@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31765>
 2024-10-24 08:17:11 +00:00
Samuel Pitoiset be81c8b8db radv: fix initializing the HTILE buffer on transfer queue 
When only of the depth/stencil aspects is used, RADV dispatches a
compute shader to initialize the HTILE buffer. But dispatching on SDMA
just hangs and the only way to initialize the HTILE buffer is to clear
both aspects using a memory fill operation.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31803>
 2024-10-24 06:25:18 +00:00
Tapani Pälli dcb88ea4ab anv/iris: add note about Wa_18039438632 for RT flush after SBA 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31801>
 2024-10-24 04:29:56 +00:00
Paulo Zanoni c0bceaf057 brw: don't emit instruction to add zero in spilling code 
When the spill_offset is zero, don't emit an instruction that adds
zero.

Results on MTL:

- Shaders:
instructions helped:   shaders/blender/581.shader_test FS SIMD8:         6760 -> 6759 (-0.01%) (scheduled: none)
instructions helped:   shaders/blender/1017.shader_test FS SIMD8:        6760 -> 6759 (-0.01%) (scheduled: none)
instructions helped:   shaders/blender/1045.shader_test FS SIMD8:        6474 -> 6473 (-0.02%) (scheduled: none)
instructions helped:   shaders/blender/723.shader_test FS SIMD8:         6458 -> 6457 (-0.02%) (scheduled: none)
instructions helped:   shaders/blender/1042.shader_test FS SIMD8:        6458 -> 6457 (-0.02%) (scheduled: none)
instructions helped:   shaders/blender/917.shader_test FS SIMD8:         4900 -> 4897 (-0.06%) (scheduled: none)
instructions helped:   shaders/blender/455.shader_test FS SIMD8:         4832 -> 4829 (-0.06%) (scheduled: none)

cycles helped:   shaders/blender/917.shader_test FS SIMD8:         891856 -> 891832 (<.01%) (scheduled: none)
cycles helped:   shaders/blender/455.shader_test FS SIMD8:         894692 -> 894660 (<.01%) (scheduled: none)

total instructions in shared programs: 1596934 -> 1596923 (<.01%)
instructions in affected programs: 42642 -> 42631 (-0.03%)
helped: 7
HURT: 0

- Fossils:

Instrs: 151744378 -> 151741213 (-0.00%)
Cycle count: 16007811131 -> 16007643963 (-0.00%); split: -0.00%, +0.00%

Totals from 1353 (0.21% of 632545) affected shaders:
Instrs: 3925143 -> 3921978 (-0.08%)
Cycle count: 2292838118 -> 2292670950 (-0.01%); split: -0.01%, +0.00%

 RELATIVE IMPROVEMENTS - Instrs                                      Before     After      Delta      Percentage
 mesa/benchmarks/gravity_mark/3e9c48cebaddf012/cs/0                  1947       1941       -6         -0.31%
 mesa/steam-native/red_dead_redemption2/571534e21fb7bd2a/fs.8/0      3431       3421       -10        -0.29%
 mesa/steam-dxvk/batman_arkham_city_goty/d783eacc9ebe324d/fs.8/0     717        715        -2         -0.28%
 mesa/steam-dxvk/batman_arkham_city_goty/14e0878a6a9605c9/fs.8/0     724        722        -2         -0.28%
 mesa/steam-dxvk/batman_arkham_city_goty/d859c2ae858269dc/fs.8/0     744        742        -2         -0.27%
 mesa/steam-dxvk/total_war_warhammer3/18b9d4a3b1961616/vs/0          1539       1535       -4         -0.26%
 mesa/steam-dxvk/total_war_warhammer3/a21827ce57dc0e29/vs/0          1539       1535       -4         -0.26%
(and a bunch of others where the delta is -2, -4 or -6)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31694>
 2024-10-23 20:19:48 +00:00
Adam Jackson 858eb18952 glx: Fix the GLX_EXT_swap_control_tear drawable attributes 
GLX_SWAP_INTERVAL_EXT is always positive, GLX_LATE_SWAPS_TEAR_EXT is how
you tell whether the drawable is set to do it. This aligns us with the
spec and NVIDIA's GLX.

Closes: mesa/mesa#10193
Fixes: 5e9e457383 glx/dri3: Implement GLX_EXT_swap_control_tear
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31655>
 2024-10-23 19:55:53 +00:00
Georg Lehmann a4b179e445 aco/ssa_elimination: don't avoid saving exec when optimizing branching sequence 
insert_exec_mask will no longer use s_and_saveexec if there was a previous copy
from a sgpr to exec, so this code path is no longer taken.

No Foz-DB changes.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31567>
 2024-10-23 19:34:53 +00:00
Georg Lehmann d2dcaf1f5e aco/insert_exec: reuse old exec temp instead using s_and_saveexec 
This means the v_cmpx optimization in ssa_elimination no longer
needs to insert a copy to save exec.

Foz-DB Navi31:
Totals from 13816 (17.40% of 79395) affected shaders:
Instrs: 23694267 -> 23670199 (-0.10%); split: -0.11%, +0.01%
CodeSize: 124559288 -> 124457508 (-0.08%); split: -0.09%, +0.01%
SpillSGPRs: 5324 -> 5354 (+0.56%); split: -1.00%, +1.56%
Latency: 207245846 -> 207213681 (-0.02%); split: -0.03%, +0.01%
InvThroughput: 35442657 -> 35437220 (-0.02%); split: -0.02%, +0.01%
VClause: 444672 -> 444670 (-0.00%); split: -0.00%, +0.00%
SClause: 639419 -> 639373 (-0.01%); split: -0.04%, +0.03%
Copies: 1529008 -> 1515871 (-0.86%); split: -1.02%, +0.16%
Branches: 557201 -> 557701 (+0.09%); split: -0.00%, +0.09%
PreSGPRs: 682840 -> 686048 (+0.47%)
VALU: 13978010 -> 13978032 (+0.00%); split: -0.00%, +0.00%
SALU: 2214600 -> 2197061 (-0.79%); split: -0.81%, +0.02%
VOPD: 5561 -> 5560 (-0.02%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31567>
 2024-10-23 19:34:53 +00:00
Georg Lehmann 0471522377 aco/insert_exec: reuse old exec temp in loop pre-header 
Avoid an exec copy.

Foz-DB Navi31:
Totals from 2315 (2.92% of 79395) affected shaders:
Instrs: 9082831 -> 9058990 (-0.26%); split: -0.27%, +0.00%
CodeSize: 48017244 -> 47858064 (-0.33%); split: -0.34%, +0.01%
SpillSGPRs: 1680 -> 1684 (+0.24%); split: -0.48%, +0.71%
Latency: 109511718 -> 109525041 (+0.01%); split: -0.01%, +0.02%
InvThroughput: 20287085 -> 20289370 (+0.01%); split: -0.00%, +0.02%
VClause: 192259 -> 192260 (+0.00%)
SClause: 234082 -> 234124 (+0.02%); split: -0.01%, +0.03%
Copies: 667271 -> 645577 (-3.25%); split: -3.27%, +0.02%
Branches: 264086 -> 264088 (+0.00%)
PreSGPRs: 136831 -> 136966 (+0.10%)
VALU: 5234735 -> 5234740 (+0.00%); split: -0.00%, +0.00%
SALU: 949283 -> 927327 (-2.31%); split: -2.32%, +0.01%
VOPD: 1529 -> 1535 (+0.39%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31567>
 2024-10-23 19:34:53 +00:00
Georg Lehmann 31f62a6123 aco/insert_exec: don't always reset top exec 
This allows to re-use previous temporaries in case exec was restored
from a Temp, rather than having to create a new copy of exec.

Foz-DB Navi31:
Totals from 545 (0.69% of 79395) affected shaders:
Instrs: 216563 -> 215698 (-0.40%)
CodeSize: 1183536 -> 1180076 (-0.29%)
Latency: 1135269 -> 1135294 (+0.00%); split: -0.00%, +0.00%
Copies: 11933 -> 11072 (-7.22%)
SALU: 18990 -> 18129 (-4.53%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31567>
 2024-10-23 19:34:53 +00:00
Georg Lehmann 4f04e6f0c4 aco/insert_exec: avoid phis for masks in exec 
Exec always contains the same value as the top of stack, even if the
top of stack is a temporary/constant. So if the predecessors have different
top of stack operands, don't insert a phi and use exec as the new top of stack.

No Foz-DB changes.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31567>
 2024-10-23 19:34:53 +00:00
Georg Lehmann 0338bb9ae8 aco/ssa_elimination: also optimize branching sequence with s_and without saveexec 
insert_exec will start using this in the future, handle it the same
just without the path to save exec before the v_cmpx instruction.

No Foz-DB changes.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31567>
 2024-10-23 19:34:53 +00:00
Lionel Landwerlin 68a372f6ce anv: use UINT32_MAX to be consistent 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Lionel Landwerlin b4ae8cf381 anv: reemit push constants on pipeline changes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02294961ee ("anv: stop using a binding table entry for gl_NumWorkgroups")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12058
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Lionel Landwerlin 7d9449c873 anv: fix missing inline parameter emission 
Should only impact Xe2+

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02294961ee ("anv: stop using a binding table entry for gl_NumWorkgroups")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Lionel Landwerlin 3a5b9ee59e anv: fix binding table entry count for compute shaders 
We're not using a binding table entry anymore for num_workgroups.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02294961ee ("anv: stop using a binding table entry for gl_NumWorkgroups")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Chia-I Wu fc2aecd2c9 panvk: fix texture size/levels/samples query 
Fix an off-by-one for user sets in load_resource_deref_desc.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31794>
 2024-10-23 18:31:22 +00:00
Eric Engestrom 1cb4378479 zink+turnip/ci: update a750 results 
These are regressions, but impossible to bisect since everything was
completely broken for ages and no test could run at all.

A commit in the range 834b919f...02269223 fixed it, and we now have
results, so let's update the results so that we can see future
unexpected results!

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31806>
 2024-10-23 18:09:28 +00:00
Martin Krastev 80233f5a88 svga/ci: enable vmware farm 
Enable farm after DUT maintenance.

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31800>
 2024-10-23 17:12:17 +00:00
Simon Perretta 981ddec633 pvr: Make Vulkan driver depend only on nir headers, not library 
Avoids linking issues when building with the compiler.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Simon Perretta c1c71b93bf pvr: rename pds unused reg constant 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Simon Perretta 84a610db30 pvr: Inline xxhash header functions 
Avoids a build error under certain configs.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Simon Perretta ac48e83af1 pvr: Add missing include for FALLTHROUGH 
Noticed with a newer version of gcc.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Simon Perretta b882cb2d90 pvr: Rescope msaa_mode 
Removes an unnecessary dependency on the compiler.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Frank Binns 1612255de6 pvr: ensure stencil clear value fits TA_STATE_ISPA.sref field 
If the stencil clear value was larger than the maximum supported by the hardware
(255) then it would end up corrupting other fields in TA_STATE_ISPA. The Vulkan
1.0.266 spec says for VkClearDepthStencilValue:

  "stencil is the clear value for the stencil aspect of the depth/stencil
   attachment. It is a 32-bit integer value which is converted to the
   attachment’s format by taking the appropriate number of LSBs."

As such, mask the clear value when packing TA_STATE_ISPA.

Fixes a number of GLES tests, including:
  dEQP-GLES2.functional.depth_stencil_clear.*stencil_scissored*
  dEQP-GLES2.functional.fragment_ops.stencil.*
  dEQP-GLES3.functional.depth_stencil_clear.*stencil_scissored*
  dEQP-GLES3.functional.fragment_ops.stencil.*

Fixes: 821c6b9342 ("pvr: Implement depth/stencil/depth+stencil attachment...")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Frank Binns e8cbfa2a57 pvr: add handling for retry error in pvr_srv_rgx_kick_compute2() 
Speculative fix following similar fixes to pvr_srv_rgx_kick_render2() and
pvr_srv_rgx_submit_transfer2().

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Frank Binns a186e28476 pvr: add handling for retry error in pvr_srv_rgx_submit_transfer2() 
The caller of pvr_srv_rgx_submit_transfer2() handles VK_NOT_READY, but
pvr_srv_rgx_submit_transfer2() would never return this error as it was missing
handling for retry errors returned by the
PVR_SRV_BRIDGE_RGXTQ_RGXSUBMITTRANSFER2 bridge call. This resulted in
pvr_srv_rgx_submit_transfer2() returning VK_ERROR_OUT_OF_DEVICE_MEMORY, which
was treated as a device lost error by callers further up the stack.

Fixes a hang seen with a release/debugoptimized build when running
KHR-GLES3.copy_tex_image_conversions.required.cubemap_negy_cubemap_negy as part
of a batch of tests.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Iliyan Dinev eb77cad906 pvr: handle PVR_SRV_ERROR_RETRY pvr_srv_rgx_kick_render2() 
ret.error wasn't being checked, so the driver incorrectly returned OOM state.

Fixes GLES test:
  dEQP-GLES2.functional.fragment_ops.stencil.zero_stencil_fail

Signed-off-by: Iliyan Dinev <iliyan.dinev@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Frank Binns 2210e7ab4f pvr: remove set but not used struct member 
Use of 'in_render_pass' was removed in 80f864cd23 ("pvr: Use common queue
submit implementation").

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Luigi Santivetti 9651d73671 pvr: really free memory in subpass render init 
Fixes: 10b6a0d567 ("pvr: Add support for generating render pass hw setup data.")
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Luigi Santivetti b8e0c15531 pvr: for fragment stages only do not insert a barrier 
If within a render pass, only insert a mid fragment barrier if needed for
stencil load/store.

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Luigi Santivetti 35f824fb07 pvr: fix when to emit ppp state uniform base address 
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Oskar Rundgren 703f3e902c pvr: improve buffer copy format selection 
Take the source and destination address alignment into account when selecting
the pixel format / texel width. This avoids the transfer job code having to
handle an unaligned copy and, as a result, trying to encode a value that is too
large for the maxclip_x field in PBESTATE_REG_WORD1.

Fixes the following test cases:
  dEQP-GLES2.functional.vertex_arrays.single_attribute.offset.buffer_4_32_fixed2_vec2_dynamic_draw_quads_256
  dEQP-GLES2.functional.vertex_arrays.single_attribute.offset.buffer_4_8_fixed2_vec2_dynamic_draw_quads_256

Signed-off-by: Oskar Rundgren <oskar.rundgren@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Iliyan Dinev 1d0f23752c pvr: fix mipmap alignment for non-32bpp textures 
There is no alignment necessary between mip levels.

Fixes test cases:
  dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_fastest
  dEQP-GLES2.functional.texture.mipmap.2d.generate.a8_non_square_nicest
  dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_fastest
  dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_nicest
  dEQP-GLES3.functional.texture.mipmap.2d.generate.a8_non_square_fastest
  dEQP-GLES3.functional.texture.mipmap.2d.generate.a8_non_square_nicest
  dEQP-GLES3.functional.texture.mipmap.2d.generate.l8_non_square_fastest
  dEQP-GLES3.functional.texture.mipmap.2d.generate.l8_non_square_nicest

Fixes: 8991e64641 ("pvr: Add a Vulkan driver for Imagination Technologies...")
Signed-off-by: Iliyan Dinev <iliyan.dinev@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Frank Binns fa889ffec7 pvr: fix use of uninitialised value when setting up tex info swizzle 
Resolves the following valgrind issue when running GLES CTS:

  ==8318== Conditional jump or move depends on uninitialised value(s)
  ==8318==    at 0x72AE91C: vk_format_to_pipe_format (vk_format.c:263)
  ==8318==    by 0x7051EE7: vk_format_description (vk_format.h:176)
  ==8318==    by 0x7052CFB: pvr_get_format_swizzle (pvr_formats.c:701)
  ==8318==    by 0x708CC2F: pvr_init_tex_info (pvr_query_compute.c:454)
  ==8318==    by 0x708D887: pvr_add_query_program (pvr_query_compute.c:663)
  ==8318==    by 0x708B9BB: pvr_CmdCopyQueryPoolResults (pvr_query.c:535)
  ==8318==    by 0x607E68F: copy_pool_results_to_buffer (zink_query.c:782)
  ==8318==    by 0x607EB37: update_qbo (zink_query.c:853)
  ==8318==    by 0x607FA17: zink_get_query_result (zink_query.c:1145)
  ==8318==    by 0x5E82987: tc_get_query_result (u_threaded_context.c:1283)
  ==8318==    by 0x59A7543: get_query_result (queryobj.c:297)
  ==8318==    by 0x59A78A7: _mesa_check_query (queryobj.c:388)

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Luigi Santivetti 1b67637fa0 pvr: fix calculation for textures z position fractional part 
The fractional part of the z position will only be used with linear or bi-linear
filtering. Otherwise it is safe to discard the original fractional value and
reset it to 0.5.

Fixes: 480bdff4b5 ("pvr: Add support to process transfer and blit cmds")
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00
Frank Binns c1bd0deb97 pvr: fix bo refcounting for imported buffers 
When importing the same dma-buf multiple times, the kernel will return us the
same GEM handle each time. This means that if we close the GEM handle for one BO
we'll end up making the handle invalid for all BOs. The driver wasn't taking
this into account and was therefore creating a new BO each time a dma-buf was
imported, meaning we could end up with multiple BOs with the same GEM
handle. Fix this by creating a single BO per GEM handle and taking an additional
reference on a BO when the kernel returns an existing GEM handle.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
 2024-10-23 16:47:34 +00:00