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10101 Commits

Author SHA1 Message Date
Friedrich Vock a418ab6654 radv: Correct accel struct header size 
The size was changed when adding metadata but not updated here.

Fixes: 07eceb4f ("radv: Add metadata to acceleration structures")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18680>
 2022-09-20 14:20:00 +00:00
Samuel Pitoiset 19eec024d2 radv,aco: do not compact MRTs if the pipeline uses a PS epilog 
We can't detect color attachment without exports when compiling a PS
epilog, so we can't compact MRTs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18514>
 2022-09-20 13:12:49 +00:00
Rhys Perry 6df5ff7f19 aco: DCE ra_ctx::defs_done 
This was used to distinguish definitions fixed before and during RA, but
it seems it isn't used anymore.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18547>
 2022-09-20 12:24:03 +00:00
Samuel Pitoiset 0f88f57223 radv: allow to build the main FS in a graphics pipeline library 
Corner cases like implicit gl_PrimitiveID are currently broken and
will be fixed later, but the general case should work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18516>
 2022-09-20 11:53:38 +00:00
Samuel Pitoiset e529745be3 radv: do not link shaders when the next stage is unknown 
With GPL, it's possible to build the pre-rasterization stages separately
from the fragment stage. Implicit IO (like gl_PrimitiveID) between the
last pre-rast stage and the FS will be addressed later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18516>
 2022-09-20 11:53:38 +00:00
Marcin Ślusarz 037404b441 nir, anv, hasvk, radv: pull uses_wide_subgroup_intrinsics into shader_info 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
 2022-09-20 10:19:21 +00:00
Samuel Pitoiset 704ef1fd3b radv,aco: lower barycentric_at_sample in NIR 
fossils-db (NAVI21):
Totals from 158 (0.12% of 134913) affected shaders:
CodeSize: 569456 -> 568824 (-0.11%)

Only Control seems affected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
 2022-09-20 09:52:37 +00:00
Samuel Pitoiset 9f0b4da875 radv: run nir_opt_cse before lowering FS intrinsics 
Otherwise, there might be redundant barycentric_at_sample intrinsics
that will be lowered and this will increase code size.

No fossils-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
 2022-09-20 09:52:37 +00:00
Samuel Pitoiset 7e433e25c8 radv: add nir_intrinsic_load_sample_positions_amd in the ABI 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
 2022-09-20 09:52:37 +00:00
Bas Nieuwenhuizen 266fe31666 ac/surface: Fix some warnings. 
../mesa/src/amd/common/ac_surface.c:2324:48: warning: implicit conversion from enumeration type 'AddrResourceType' (aka 'enum _AddrResourceType') to different enumeration type 'enum gfx9_resource_type' [-Wenum-conversion]
   surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
                              ~ ~~~~~~~~~~~~~~~^~~~~~~~~~~~
../mesa/src/amd/common/ac_surface.c:3046:38: warning: implicit conversion from enumeration type 'const enum gfx9_resource_type' to different enumeration type 'AddrResourceType' (aka 'enum _AddrResourceType') [-Wenum-conversion]
   input.resourceType = surf->u.gfx9.resource_type;
                      ~ ~~~~~~~~~~~~~^~~~~~~~~~~~~
../mesa/src/amd/common/ac_surface.c:3069:38: warning: implicit conversion from enumeration type 'const enum gfx9_resource_type' to different enumeration type 'AddrResourceType' (aka 'enum _AddrResourceType') [-Wenum-conversion]
   input.resourceType = surf->u.gfx9.resource_type;

The enums are compatible so lets just add some casts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18694>
 2022-09-20 09:25:09 +00:00
Vinson Lee 97d307406b radv: Use count_tes_user_sgprs return value. 
Fix defect reported by Coverity Scan.

Useless call (USELESS_CALL)
side_effect_free: Calling count_tes_user_sgprs(key) is only useful for
its return value, which is ignored.

Fixes: 8253ec3855 ("radv: add shader arguments for dynamic patch control points")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18659>
 2022-09-20 06:14:47 +00:00
Qiang Yu 4d15a06dee radeonsi: implement nir_intrinsic_load_streamout_buffer_amd 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17456>
 2022-09-20 05:41:50 +00:00
Qiang Yu 8049edb653 radeonsi: implement nir_intrinsic_load_num_vertices_per_primitive_amd 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17456>
 2022-09-20 05:41:50 +00:00
Bas Nieuwenhuizen b2972cf410 radv: Add scratch stack to reduce LDS stack in RT traversal. 
The current stack size is a significant limiter for occupancy, and
hence we need smaller stacks in LDS.

Rhys earlier had a patch that just put the N entries closest to the
root in LDS and the rest in scratch. However, this is not ideal for
performance as most of the activity is happening away from the root,
near the leaves. Of course we can't just switch it around, as the
leaf activity likely isn't happening all the way at the end of the
stack.

So what we do is make the LDS stack kinda a ringbuffer by always
accessing it using the stack index modulo the buffer size (always
a power of two so we can efficiently mask). If we then do not have
free space in this buffer we evict the entries closest to the root
to scratch and if we hit the "bottom" of the LDS space we load from
scratch.

Some rough perf numbers for indication with Q2RTX:

| evicting | LDS entries | perf |
|----------|-------------|------|
|       no |          76 |  55% |
|       no |          32 | 100% |
|       no |          24 | 105% |
|      yes |          32 |  95% |
|      yes |          16 | 100% |
|      yes |           8 |  90% |
|      yes |           4 |  75% |

(For the case with 4 entries we need to do some extra accounting as
 a full batch may not be available to evict)

So an obvious choice is to use a stack of 16 entries.

One might wonder if Q2RTX perf is mainly good due to BVHs with very
little geometry and hence low depth, so I also did some profiling
with control. This is done with RGP instruction timing, so this is
instructions executed not weighted for enabled masks, i.e. divergence
effects included.

| game    | LDS entries | scratch action | fraction of iterations |
|---------|-------------|----------------|------------------------|
| Control |           8 |          store |                  10.3% |
| Control |           8 |          load  |                  34.8% |
| Control |          16 |          store |                  0.58% |
| Control |          16 |          load  |                  2.62% |
| Q2RTX   |          16 |          store |                  1.00% |
| Q2RTX   |          16 |          load  |                  3.07% |

So Q2RTX doesn't seem like an unreasonably good case for this
algorithm.

On the implementation side, we can always place the scratch stack at
address 0 by just reserving the scratch space, and in the case of fixed
callstack size moving that up. In the dynamic case the dynamic stack
base already takes any reserved scratch space into account.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18541>
 2022-09-20 01:39:20 +00:00
Rhys Perry 7d26fafacf radv: fix dynamic RT stack size with VGPR spilling 
VGPR spilling might cause VGPRs to be spilled at scratch offset 0, so we
can't use that.

fossil-db (Sienna Cichlid, Q2RTX and Control):
Totals from 4 (0.26% of 1524) affected shaders:
Instrs: 8734 -> 8737 (+0.03%)
CodeSize: 48492 -> 48504 (+0.02%)
Latency: 384375 -> 384369 (-0.00%)
InvThroughput: 256250 -> 256246 (-0.00%)
Copies: 1312 -> 1313 (+0.08%)
Branches: 256 -> 258 (+0.78%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18541>
 2022-09-20 01:39:20 +00:00
Bas Nieuwenhuizen ca04f968d9 radv: Use nested ifs for pushing child nodes in traversal loop. 
Avoids a bunch of overhead costs if the previous child was empty
already.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18538>
 2022-09-20 01:29:05 +02:00
Bas Nieuwenhuizen 91a4cd26b3 radv: Use constant for ray traversal exit condition. 
Make the stack base ssa def dead in the loop, can save a register.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18538>
 2022-09-20 01:29:04 +02:00
Bas Nieuwenhuizen 40a235c9a8 Revert "radv/rt: use derefs for the traversal stack" 
This reverts commit 3750663c72.

Doing things with derefs adds extra instructions for multiplying the
index with the element size, e.g.

BBF0_13:
   s_waitcnt vmcnt(0)
   v_mov_b32_e32 v27, v55
   s_mov_b32 s23, exec_lo
   v_cmpx_ne_i32_e32 -1, v27
   s_cbranch_execz _L14
BBF0_14:
   v_lshlrev_b32_e32 v48, 2, v46  <--
   ds_write_b32 v48, v27
   v_add_nc_u32_e32 v46, 32, v46
_L14:
   s_mov_b32 exec_lo, s23
   v_mov_b32_e32 v27, v54
   s_mov_b32 s23, exec_lo
   v_cmpx_ne_i32_e32 -1, v27
   s_cbranch_execz _L15
BBF0_15:
   v_lshlrev_b32_e32 v48, 2, v46 <--
   ds_write_b32 v48, v27
   v_add_nc_u32_e32 v46, 32, v46

On Q2RTC indirect lighting this saves about 2.3 VALU instructions
per loop iteration, which is ~4% of VALU instructions (we're at
58 per iteration now according to RGP).

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18538>
 2022-09-20 01:29:04 +02:00
Bas Nieuwenhuizen 85ca0b12a2 radv: Store top of stack in a register. 
Saves a bunch of processing and a lot of LDS traffic.

Improves perf of the indirect lighting RT pass in Q2RTX by ~3%. This
is mostly due to the -5% VALU instructions and -25% LDS instructions.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18538>
 2022-09-20 01:29:04 +02:00
Bas Nieuwenhuizen f7f48251b0 radv: Don't flatten bottom AS exit if statement. 
The flattening by ACO is more efficient than the nir condmask.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18538>
 2022-09-20 01:29:04 +02:00
Kai Wasserbäch 06504254ce fix: ac/llvm: unused variable ‘offset’ [-Wunused-variable] 
Only used in debug builds.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18643>
 2022-09-19 22:02:16 +00:00
James Park b7d4897df9 meson,amd: Remove Windows libelf wrap 
Functionality isn't worth the maintenance cost.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18478>
 2022-09-19 12:51:12 +00:00
Rhys Perry e122d95d73 radv: remove unnecessary .align_mul=4 
The builders can pick a default using the component size.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Rhys Perry ee1a75bd74 radv: use nir_ubfe_imm 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Rhys Perry 272d37fa72 radv: shrink zero-initialization in vkCmdSetVertexInputEXT 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Rhys Perry 891cb799aa radv: disable EXT_vertex_input_dynamic_state when using DGC 
This simplifies the DGC path and removes some untested code. The only user
of the partial DGC implementation (vkd3d-proton) doesn't use
EXT_vertex_input_dynamic_state.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Samuel Pitoiset 299d294304 Revert "radv: upload the PS epilog in the existing pipeline BO" 
This is completely broken because the PS epilog has refcount and
radv_upload_shaders() updates its VA.

This reverts commit 7c34b31db2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18632>
 2022-09-16 11:38:28 +00:00
Qiang Yu 074f3216f2 ac/nir/ngg: support gs streamout 
Port from radeonsi.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu 3fe8f88124 ac/nir/ngg: support multi stream per output slot for gs 
radeonsi may pack multi stream output to same slot.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu c25564b552 ac/nir/ngg: ngg_gs_load_out_vtx_primflag support stream 
Streamout need primflag for any stream.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu 5ec79f9899 ac/nir/ngg: nogs support streamout 
Port from radeonsi.

Works on both GFX11 and GFX10. Although GFX10 can do atomic
GDS add on all threads, now we just disable the NGG streamout
for GFX10, so it's OK.

There's a difference for the GFX11 implementation with radeonsi
that we do all 4 buffer/stream info calc on a single thread.
It's just because this is simple, we need to update GDS on a
single thread anyway, and streamout is not that performance
critical to loss a small amount of instruction. We may change
to a better implementation when using register based streamout.

When streamout enabled, ES threads need to save all vertex
attributes to LDS besides position. This is because we don't
know where in the streamout buffer to export the attributes to
and wheter there are space in the streamout buffer.

Streamout is done in primitives, so we need to check if there
is space and where the current primitive should be written to
by GDS atomic add, then in GS threads do the streamout.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu 30c7608516 ac/nir/ngg: cleanup prim id to prepare for streamout 
Streamout also need barrier after culling, so move the
prim id barrier up to after culling.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu 6762bc8bd6 ac/llvm: implement nir_intrinsic_ordered_xfb_counter_add_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu 1119e06a45 nir,ac/llvm: add nir_intrinsic_load_ordered_id_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Samuel Pitoiset f5ba4e855e radv: do not remove PSIZ for VS when the topology is unknown 
When compiling only the pre-rast stages in a library, the input
assembly state might not be present and the topology would be 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18519>
 2022-09-16 08:22:16 +00:00
Samuel Pitoiset 7f91555d4c radv: enable the VS prologs cache if graphicsPipelineLibrary is enabled 
GPL will re-use most of the VS prologs code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18519>
 2022-09-16 08:22:16 +00:00
Samuel Pitoiset c199a5160a radv: bind the VS input state for prologs created with GPL 
If we have a VS that needs a prolog without using the dynamic state,
that means that it comes from a library, so we can overwrite the
cmdbuf VS input state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18519>
 2022-09-16 08:22:16 +00:00
Samuel Pitoiset 0feab7b9cf radv: prepare the VS input state for prologs created with GPL 
This state will be bound at pipeline bind time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18519>
 2022-09-16 08:22:16 +00:00
Samuel Pitoiset fdfa59d7bf radv: rename radv_pipeline_key::vs::dynamic_vs_input to has_prolog 
With GPL it's possible to create VS prologs without this dynamic state,
so it seems better to rename.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18519>
 2022-09-16 08:22:16 +00:00
Samuel Pitoiset 57b3bff41a radv: disable VK_EXT_graphics_pipeline_library with LLVM 
Epilogs/prologs aren't supported at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18609>
 2022-09-16 07:12:40 +00:00
Konstantin Seurer b12cc5c4fe radv: Cleanup radv_GetInstanceProcAddr 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18600>
 2022-09-15 20:50:17 +00:00
Hans-Kristian Arntzen f5b46a643f radv: Implement VK_EXT_mutable_descriptor_type. 
Trivial promotion from VALVE, just rename enums and types.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18610>
 2022-09-15 16:55:25 +00:00
Martin Roukala (né Peres) 2aa4ed16e2 radv/ci: move some tests from the renoir fail to its flake list 
This mirrors the change we made for vega10 (6bbe3c6d3) in August...
Seems like the chances of a PASS are indeed slim, but possible.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18590>
 2022-09-15 14:12:07 +00:00
Samuel Pitoiset efd8d0f6e7 radv/ci: cleanup lists of failures/flakes 
When tests are already in the flakes list, it's useless to mark them
as expected failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18592>
 2022-09-15 07:49:33 +02:00
Samuel Pitoiset 731116da1a radv: stop checking for NULL pipelines in radv_CmdBindPipeline() 
This should never happen now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
 2022-09-14 19:13:43 +00:00
Samuel Pitoiset 949d76d174 radv: stop dirtying the graphics pipeline when restoring it 
radv_CmdBindPipeline() does it already.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
 2022-09-14 19:13:42 +00:00
Samuel Pitoiset 73f1155193 radv: reset the compute pipeline when the saved one was NULL 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
 2022-09-14 19:13:42 +00:00
Samuel Pitoiset 3cceaaf5cd radv: do not bind NULL graphics pipeline when restoring the meta state 
It's invalid to bind NULL pipelines, but make sure to reset it to
its previous NULL state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
 2022-09-14 19:13:42 +00:00
Samuel Pitoiset 9ebaa62a34 radv: stop setting redundant viewport/scissor for internal operations 
Only emit them when it's needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
 2022-09-14 19:13:42 +00:00
Mike Blumenkrantz 5505811f64 radv: avoid bottlenecking on sequential sparse buffer binds 
it's more costly to submit individual sparse buffer binds than to
merge them and submit bigger binds, so try to pre-compare and flatten
out the bind array as much as possible to reduce ioctl counts

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18507>
 2022-09-14 14:40:02 +00:00