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Author SHA1 Message Date
Christian Gmeiner ce2fc866ec etnaviv: Move halti determination to drm 
The ideal place to store the halti value is in struct etna_core_info.
Let's put it there and the determination of it into etna_gpu_new(..).
This makes it possible to reuse the halti level outside of gallium.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30394>
 2024-08-13 22:15:22 +00:00
Michael Cheng 0324d4bcf5 anv: move trace logic to batch_emit_pipe_control_write 
Move trace logic from cmd_buffer_apply_pipe_flushes down to
genX(batch_emit_pipe_control_write).

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30623>
 2024-08-13 21:42:43 +00:00
José Roberto de Souza 600d88ab3c intel: Remove INTEL_ENGINE_CLASS_COMPUTE and INTEL_ENGINE_CLASS_COPY parameters 
It has been a while that the GuC version with the compute engine fix
was released, same for the KMD uAPI to query the GuC firmware version.
So at this point this parameters do more harm than good.

Also just setting those don't enable the async compute and copy engines
this is not enabled by default on i915.

If user wants to disable or enable usage of those engines a better
approach would be use ANV_QUEUE_OVERRIDE.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30593>
 2024-08-13 21:15:31 +00:00
José Roberto de Souza 61e3a680a4 anv: Extend ANV_QUEUE_OVERRIDE to blit count 
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30593>
 2024-08-13 21:15:31 +00:00
José Roberto de Souza 92f4008473 anv: Disable sparse even on Xe KMD with ANV_SPARSE 
ANV_SPARSE had no effect on Xe KMD.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30593>
 2024-08-13 21:15:31 +00:00
Matt Turner 05dc4eb536 util: Force emission of stack frame in stack unit test 
The `capture_not_overwritten` unit test captures and compares two
backtraces -- one from inside a call to `func_c` and one outside -- and
confirms that they are not identical. That is, that `func_c` is in the
backtrace.

On 32-bit x86, without `-fno-omit-frame-pointer`, the function will not
emit a stack frame. As a result, the unit test fails.

The fix is to compile `func_c` with the flag `-fno-omit-frame-pointer`
to prevent the compiler from optimizing out the stack frame which is
otherwise unneeded.

Bug: https://bugs.gentoo.org/823774
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4091
Fixes: d0d14f3f64 ("util: Add unit test for stack backtrace caputure")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30622>
 2024-08-13 20:35:23 +00:00
Matt Turner b3430a7bb8 util: Add ATTRIBUTE_OPTIMIZE(flags) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30622>
 2024-08-13 20:35:23 +00:00
Sagar Ghuge 83c2524124 intel/compiler: Adjust trace ray control field on Xe2 
Bspec 64643: Structure_TraceRayPayload::Trace Ray Control

Bit field moved from 9-8 to 10-8 on Xe2.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30600>
 2024-08-13 20:02:24 +00:00
Sagar Ghuge c3c62e493f intel/compiler: Ray query requires write-back register 
Bspec 57508: Structure_SIMD16TraceRayMessage:: RayQuery Enable

   "When this bit is set in the header, Trace Ray Message behaves like a
   Ray Query. This message requires a write-back message indicating
   RayQuery for all valid Rays (SIMD lanes) have completed."

If we don't pass the write-back register, somehow it was stepping on
over R0 register and can mess up the scratch space accesses which could
potentially lead to GPU hang. It can be noticed while running it under
simulator trace.

send.rta (16|M0)         null     r124  r126:1  0x0            0x02000100           {$15} // wr:1+1, rd:0; simd16 trace ray
R0 = 00000001 00000000 00000000 00000001 00000000 00000000 00000001 00000000 00000000 00000001 00000000 00000000 00000001 00000000 00000000 00000001

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30600>
 2024-08-13 20:02:24 +00:00
Mike Blumenkrantz a7f64c6203 zink: fix partial update handling 
* the damage region was not being used correctly (this is a normal rect)
* use_damage was never unset at frame boundary
* original renderArea was never re-set

Fixes: 3d38c9597f ("zink: hook up KHR_partial_update")

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30625>
 2024-08-13 15:26:27 +00:00
Job Noorman 2260a4bbba ir3: fix spill/reload split src/dst regs 
When splitting spills/reloads into to multiple separate spills/reloads,
the src/dst registers where not adjusted. This caused the separate
instructions too all refer to the same register.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30613>
 2024-08-13 14:59:23 +00:00
Samuel Pitoiset 092b0ecc2e ci: add GFX1150 support to radv-fossils 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30620>
 2024-08-13 13:17:17 +00:00
Samuel Pitoiset 99b12b2a65 amd/drm-shim: add GFX1150 support 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30620>
 2024-08-13 13:17:17 +00:00
Samuel Pitoiset 2b3cf188de amd/drm-shim: add missing GC_11_5_0 family 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30620>
 2024-08-13 13:17:17 +00:00
Alyssa Rosenzweig fd63356268 r300: switch to derivative intrinsics 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30572>
 2024-08-13 12:45:12 +00:00
Alyssa Rosenzweig 772e6d61b9 ntt: switch to derivative intrinsics 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30572>
 2024-08-13 12:45:12 +00:00
Pavel Ondračka 9966365fe0 ttn: switch to derivative intrinsics 
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30572>
 2024-08-13 12:45:12 +00:00
Alyssa Rosenzweig 5f437aa24d elk: fix compute shader derivatives 
derivatives are not fs only so move to be with the rest of subgroup ops.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11674
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30634>
 2024-08-13 12:19:30 +00:00
Iago Toral Quiroga ad9ff707ce broadcom: drop backend implementation of nir_op_ufind_msb 
We can have NIR do this for us now that we have uclz.

Suggested by Georg Lehmann.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30614>
 2024-08-13 13:16:18 +02:00
Iago Toral Quiroga 35a10f5d5a broadcom: implement nir_op_uclz 
This enables some algebraic optimizations.

No changes in shader-db, but it does cause some CTS tests to
produce less instructions.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30614>
 2024-08-13 13:16:11 +02:00
Lionel Landwerlin aaff191356 brw/rt: fix ray_object_(direction|origin) for closest-hit shaders 
When closest hit shader is called, the BVH object level
brw_nir_rt_load_mem_ray origin/direction is 0. What we should be using
is the ray origin/direction and apply the transform of the current
instance.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9ba7d459a3 ("intel/rt: Implement the new ray-tracing system values")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30578>
 2024-08-13 10:28:50 +00:00
Karol Herbst 7935623126 rusticl/kernel: simplify adding internal kernel args 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst d72cc037f2 rusticl/kernel: move CompiledKernelArg decleration above the impl block 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst 24ea5a756c rusticl/kernel: add KernelArgType::is_opaque 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst d26d17bbaf rusticl/kernel: big kernel arg rework 
The main change here is that instead of having two vectors for API and
internal arguments, there is just one per built kernel.

Some of the API level information is still in its own structure and
referenced by the above mentioned merged vector, but with this change each
device and also each kernel variant can have arguments placed at different
locations or even have a different set of arguments.

This rework will be necessary to add kernel variants in a non messy way.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst 0b98e47d83 rusticl/kernel: move serialization code of KernelArgType 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst 2645ba6942 rusticl/kernel: rename InternalKernelArgType to CompiledKernelArgType 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst 3cc3ba2e8f rusticl/kernel: make KernelArg::offset and KernelArg::binding proper u32 values 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst b142bee150 rusticl/kernel: make CompiledKernelArg::offset a u32 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst e69ad5ff69 rusticl/kernel: remove CompiledKernelArg::size 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst 3ddc2b536d rusticl/kernel: rename InternalKernelArg to CompiledKernelArg 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst 16a2808299 rusticl/kernel: move kernel size into Constant arg type 
It's the only argument type with an actual size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Karol Herbst 0cfcd2ff83 rusticl/memory: fix sampler argument size check 
Not entirely sure why this hasn't caused any problems...

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30602>
 2024-08-13 10:07:03 +00:00
Pavel Ondračka 1cad339409 r300: bias presubtract fix 
We need to double check that the source is indeed constant before
looking at the constant type.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Fixes: 0508db9155
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29893>
 2024-08-13 08:52:45 +00:00
Samuel Pitoiset 5d367aba7b radv: stop re-initializing HTILE for non-compressed to compressed transitions 
Decompressing HTILE should also reset the HTILE metadata to initial
state which means that re-initializing it for non-compressed to
compressed transitions is redundant.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30122>
 2024-08-13 06:16:03 +00:00
Alyssa Rosenzweig f690592692 agx: lower exact frcp 
the hardware is off by 1 ULP. fixes nir_lower_idiv brokenness.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig 6405153a07 asahi: switch to block based compute blitter 
This fixes the compute blitter with compression in the general case, and then
flips the switch since the compute blitter is faster / less buggy than the
traditional path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig 94cf7de88f asahi: pack imageblock words for compute 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig e3e82f7a6c agx: add a comment about an unknown bit 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig 8b29f0a762 agx: handle explicit coordinate tib instructions 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig f706079dc5 agx: allow st_tile in compute shaders 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig 9b39c5427f agx: plumb imageblock stride 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig b9eff53daa nir: add image_block_size_per_thread_agx info 
This is like shared_size but for spatial data instead, for compute shaders that
use the tilebuffer.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 19:11:23 -04:00
Alyssa Rosenzweig e754e54f88 nir: model AGX explicit coordinate intrinsics 
I don't know what Apple calls these, so we're using the name "explicit
coordinates".

AGX has instructions for loading/stores register <---> tilebuffer ---> storage
images. Usually these are used in the fragment shader and end-of-tile shader to
implement colour attachments, with implicitly specified coordinates based on the
shader stage. However they can also be used in compute shaders with explicitly
specified coordinates ("imageblocks" in Apple parlance). Model this in NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 18:46:31 -04:00
Alyssa Rosenzweig 290820e8b0 agx: fix block_image_store indirect ts 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 18:46:31 -04:00
Alyssa Rosenzweig 7de5d51f16 hk: advertise KHR_sampler_ycbcr_conversion 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 18:46:31 -04:00
Alyssa Rosenzweig 001a9e20c4 hk: denouveau 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 18:46:31 -04:00
Alyssa Rosenzweig c50e0934e7 agx: let if-fusing opts interact 
total instructions in shared programs: 2115031 -> 2114800 (-0.01%)
instructions in affected programs: 46937 -> 46706 (-0.49%)
helped: 147
HURT: 30
Instructions are helped.

total alu in shared programs: 1669893 -> 1669655 (-0.01%)
alu in affected programs: 38134 -> 37896 (-0.62%)
helped: 147
HURT: 28
Alu are helped.

total fscib in shared programs: 1666017 -> 1665779 (-0.01%)
fscib in affected programs: 38134 -> 37896 (-0.62%)
helped: 147
HURT: 28
Fscib are helped.

total bytes in shared programs: 14059380 -> 14057364 (-0.01%)
bytes in affected programs: 306294 -> 304278 (-0.66%)
helped: 147
HURT: 28
Bytes are helped.

total regs in shared programs: 656483 -> 656491 (<.01%)
regs in affected programs: 257 -> 265 (3.11%)
helped: 3
HURT: 4
Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 18:46:31 -04:00
Alyssa Rosenzweig 64239ac12c agx: fuse not into if 
total instructions in shared programs: 2115466 -> 2115031 (-0.02%)
instructions in affected programs: 68776 -> 68341 (-0.63%)
helped: 222
HURT: 5
Instructions are helped.

total alu in shared programs: 1670328 -> 1669893 (-0.03%)
alu in affected programs: 54224 -> 53789 (-0.80%)
helped: 222
HURT: 5
Alu are helped.

total fscib in shared programs: 1666452 -> 1666017 (-0.03%)
fscib in affected programs: 54224 -> 53789 (-0.80%)
helped: 222
HURT: 5
Fscib are helped.

total bytes in shared programs: 14061990 -> 14059380 (-0.02%)
bytes in affected programs: 458702 -> 456092 (-0.57%)
helped: 222
HURT: 5
Bytes are helped.

total regs in shared programs: 656515 -> 656483 (<.01%)
regs in affected programs: 432 -> 400 (-7.41%)
helped: 7
HURT: 1
Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 18:46:31 -04:00
Alyssa Rosenzweig 2b1859cd06 agx: tweak jmp_exec_none heuristic 
to make sure border colour code is skipped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30633>
 2024-08-12 18:46:31 -04:00