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5719 Commits

Author SHA1 Message Date
Kristian H. Kristensen
6b3f56f099 anv: Add stub for anv_gem_get_tiling() for Android 
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6112>
 2020-08-05 18:08:07 +00:00
Kristian H. Kristensen
ff0dbf2096 anv: Pass device to setup_gralloc0_usage for error reporting 
Otherwise it doesn't compile.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: aba57b11ee ("anv: support GetSwapchainGrallocUsage2ANDROID for Android")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6112>
 2020-08-05 18:08:07 +00:00
Iván Briano
d33f46e08b anv: fix allocation of custom border color pool 
Turns out that respecting the order of parameters is important.

Reported-by: Michael Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 5425968d2e ("anv: Implement VK_EXT_custom_border_color")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6175>
 2020-08-04 15:30:33 -07:00
Eric Anholt
023e6669cc i965: Enable vector shrinking in the vec4 backend. 
This manages to make some extra vec operations that would turn into movs
go away.

brw shader-db:
total instructions in shared programs: 3895037 -> 3893221 (-0.05%)
total cycles in shared programs: 113832759 -> 113792154 (-0.04%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6050>
 2020-08-03 21:26:45 +00:00
Jason Ekstrand
3c2a1af660 anv: Implement VK_EXT_4444_formats 
We only support the ARGB format, not the ABGR one.  Fortunately, the
ARGB is the one required by D3D11.

Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6158>
 2020-08-03 17:50:03 +00:00
Tapani Pälli
32e0f7e097 anv: toggle on VK_EXT_extended_dynamic_state 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
b9a05447a1 anv: dynamic vertex input binding stride and size support 
If pStrides or Psizes are NULL we should use the values defined by the
pipeline.

v2: fix commit message and fix the code to set explicitly if we are
    using dynamic stride/size

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
e4590c0750 anv: depth/stencil dynamic state support 
v2: code cleanup, remove extra spaces (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
f6fa4a8000 anv: add support for dynamic primitive topology change 
This is done using 3DSTATE_VF_TOPOLOGY packet that overrides topology
used in subsequent 3DPRIMITIVE commands. For gen7[5] we override the
pipeline topology when emitting draw commands.

v2: fix the way gen7[5] is handled (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
f426663f9c anv: add support for dynamic viewport and scissor with count 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
9220598b36 anv: add support for dynamic cull mode and winding order 
v2: cleanup, white space issues (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
c34d8ac26e anv: handle dynamic viewport count 
Emit 3DSTATE_CLIP during cmd_buffer_flush_state so that we can change
the max viewport count dynamically.

v2: use one common clip state as size is the same for all gens (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
11f3fb9a4e anv: consider dynamic state when creating pipeline 
Leave default state values as zero so that when we OR them later
it is only the dynamic state value that matters.

v2: code cleanup + skip topology emit in base batch
    when topology is dynamic (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
65de778e0b anv: add new dynamic states 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Tapani Pälli
2260ce6d0c anv: add VK_EXT_extended_dynamic_state but leave it disabled 
This is needed to ensure the function prototypes are declared.

v2: tweak commit message (Jason)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
 2020-08-02 17:44:54 +00:00
Matt Turner
eaf27eb512 intel/tools: Test notification subregisters 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
ac7ecd205b intel/tools: Simplify notification register handling 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
63181df09b intel/tools: Don't hardcode notification register 
Previously we parsed a src non-terminal but did nothing with it. Since
the WAIT instruction is kind of weird, in that you have to give it the
same notification subregister for both destination and source, and it
always has an exec size of 1, let's parse a destination instead of a
source. This way, we can parse a writemask rather than a swizzle in
align16 mode, and easily convert the writemask to a swizzle to create
the source register.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
90c18ec8db intel/tools: Manually set ARF register file/nr/subnr 
brw_reg::subnr is in bytes, like the subnr field in the instruction
word, but we disassemble the subregister number in units of the type.
For example g0.3<1>F would have a subnr=12.

These non-terminals produce a brw_reg and feed into other non-terminals
that call brw_reg(), where they are passed the subnr that we set here.
brw_reg()'s subnr parameter is expected to be in terms of the register
type, and it is multiplied by the type size to calculate the subnr in
bytes.

In these non-terminals, we don't know the register type yet, so we
must store the subregister number as it was given to us in the .subnr
field and let the brw_reg() constructor handle the conversion to the
canonical byte-based subnr form when it knows the type.

Before this patch, subregister numbers applied to these registers would
be multiplied with the type size twice.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
af6d6f5c43 intel/tools: Pass integers, not enums, to stride() 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
c883c482be intel/compiler: Relax SENDS regioning assertions 
The next commit fixes a mistake in the assembler and ends up running
afoul of this assertion.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
363e5ef5a5 intel/tools: Simplify dstregion 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
3d9c673c0f intel/tools: Simplify immediate handling 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
59801f07e7 intel/tools: Make writemask an integer 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
e115c499da intel/tools: Make swizzle an integer 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
3e1602cc4f intel/tools: Simplify register type handling 
Produce a brw_reg_type rather than a whole brw_reg and rename a few
non-terminals.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
2851c218e2 intel/tools: Don't allow empty type specifier 
It's preferable to require an explicit type.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
6809b93411 intel/tools: Remove stray newline 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
Matt Turner
fdfbb1ed26 intel/tools: Fix typos 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
 2020-07-31 12:59:24 -07:00
David Stevens
6c11a7994d i965/i915: Add colorspace support to YUV sampling 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6122>
 2020-07-31 07:27:03 +00:00
Boris Brezillon
025988f818 intel: Set int64_options to ~0 when lowering 64b ops 
That's more future proof than setting each bit manually. Looks like we
already miss nir_lower_ufind_msb64 because of that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5588>
 2020-07-30 16:54:24 +00:00
Boris Brezillon
bfee35b45c nir: Stop passing an options arg to nir_lower_int64() 
This information is exposed through shader->options->lower_int64_options.
Removing the extra arg forces drivers to initialize this field correctly.

This also allows us to check the int64 lowering options from each int64
lowering helper and decide if we should lower the instructions we
introduce.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5588>
 2020-07-30 16:54:24 +00:00
Marcin Ślusarz
cb19fe24d3 intel/vec4: fix out of bounds read 
NIR_MAX_VEC_COMPONENTS was bumped from 4 to 16 in a8ec4082
(2019.03.09, merged 2019.12.21)

float[4] array was added in acd7796a
(2019.06.11, merged 2019.07.11)

Found by Coverity.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3014

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Fixes: a8ec4082a4 ("nir+vtn: vec8+vec16 support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6067>
 2020-07-30 10:41:00 +00:00
Alejandro Piñeiro
62bfc700f7 vulkan/util: add struct vk_pipeline_cache_header 
Header is defined at vkGetPipelineCacheData spec, in any vulkan
version, and anv, tu and radv were using the same struct, and v3dv was
about to do the same.

Defining the same struct four times seemed odd, so let's define on a
common place.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6058>
 2020-07-30 11:44:21 +02:00
Jason Ekstrand
5c5555a862 nir: Add a find_variable_with_[driver_]location helper 
We've hand-rolled this loop 10 places and those are just the ones I
found easily.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5966>
 2020-07-29 17:38:58 +00:00
Jason Ekstrand
d70fff99c5 nir: Use a single list for all shader variables 
Instead of having separate lists of variables, roughly sorted by mode,
use a single list for all shader-level NIR variables.  This makes a few
list walks a bit longer here and there but list walks aren't a very
common thing in NIR at all.  On the other hand, it makes a lot of things
like validation, printing, etc. way simpler.  Also, there are a number
of cases where we move variables from inputs/outputs to globals and this
makes it way easier because we no longer have to move them between
lists.  We only have to deal with that if moving them from the shader to
a nir_function_impl.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5966>
 2020-07-29 17:38:58 +00:00
Jason Ekstrand
feb32f898c nir: Add a nir_foreach_uniform_variable helper 
This one's a bit more complex because it filters off only those
variables with mode == nir_var_uniform.  As such, it's not exactly a
drop-in replacement for nir_foreach_variable(var, &nir->uniforms).

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5966>
 2020-07-29 17:38:58 +00:00
Jason Ekstrand
2956d53400 nir: Add nir_foreach_shader_in/out_variable helpers 
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5966>
 2020-07-29 17:38:57 +00:00
Lionel Landwerlin
1cdd161a30 anv: fix descriptor set free 
Once we start going through the free list of the descriptor set pool,
we might use a free entry larger than the descriptor set we want to
allocate. When we free that descriptor set, we use the size of the set
rather than the size of the entry that was picked. This leads to leaks
of some amount of descriptor set pool.

This fix saves the size of the entry in the descriptor set so we know
what amount of the pool needs to freed.

v2: Don't bother adding a new size field

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3324
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6084>
 2020-07-28 14:51:15 +00:00
Jason Ekstrand
196db51fc2 anv,turnip,radv,clover,glspirv: Run nir_copy_prop before nir_opt_deref 
We're about to make the SPIR-V -> NIR path generate a bit more complex
SSA chains for certain derefs.  This will ensure we don't regress anyone
when we start making vec2's of derefs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5278>
 2020-07-23 22:43:21 -05:00
Francisco Jerez
4d73988f6f intel/ir/gen12+: Work around FS performance regressions due to SIMD32 discard divergence. 
This avoids some performance regressions on Gen12 platforms caused by
SIMD32 fragment shaders reported in titles like Dota2, TF2, Xonotic,
and GFXBench5 Car Chase and Aztec Ruins.

The most obvious pattern in the regressing shaders I identified among
these workloads is that they all had non-uniform discard statements,
which are handled rather optimistically by the current IR analysis
pass: No penalty is currently applied to the SIMD32 variant of the
shader in the form of differing branching weights like we do for other
control flow instructions in order to account for the greater
likelihood of divergence of a SIMD32 shader.

Simply changing that by giving the same treatment to discard
statements as we give to other branching instructions seemed to hurt
more than it helped on platforms earlier than Gen12, since it reversed
most of the improvement obtained from SIMD32 fragment shaders in
Manhattan for no measurable benefit in other workloads (Manhattan has
a handful of shaders with statically non-uniform discard statements
which actually perform better in SIMD32 mode due to their approximate
dynamic uniformity).  For that reason this change is applied to Gen12+
platforms only.

I've been running a number of tests trying to understand the
difference in behavior between Gen12 and earlier platforms, and most
of the evidence I've gathered seems to point at EU fusion being the
culprit: Unlike previous generations, on Gen12 EUs are arranged in
pairs which execute instructions in lockstep, giving an effective warp
size of 64 threads in SIMD32 mode, which seems to increase the
likelihood for control flow divergence in some of the affected shaders
significantly.

Fixes: 188a3659ae "intel/ir: Import shader performance analysis pass."
Reported-by: Caleb Callaway <caleb.callaway@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5910>
 2020-07-23 01:40:06 +00:00
Lionel Landwerlin
3a4024e776 anv: properly handle fence import of sync_fd = -1 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 43e8808b82 ("anv: Add support for the SYNC_FD handle type for fences")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5964>
 2020-07-22 05:07:05 +00:00
Jason Ekstrand
4d44848c47 anv: Advertise support for VK_EXT_shader_atomic_float 
We already have all of the shader code for load/store/exchange.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5992>
 2020-07-21 05:01:34 +00:00
Jason Ekstrand
675d7b19a9 intel/fs: Use the correct logical op for global float atomics 
Fixes: e644ed468f "intel/fs: Implement nir_intrinsic_global_atomic_*"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5992>
 2020-07-21 05:01:34 +00:00
Jason Ekstrand
36e6ac65c5 anv: Advertise VK_EXT_image_robustness 
We already support a superset of VK_EXT_image_robustness via
VK_EXT_robustness2.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5985>
 2020-07-20 22:30:18 +00:00
Eric Anholt
d735f075a6 intel/perf: Move perf query register programming to static tables. 
And now that they're static tables, we don't need to ralloc a copy in
non-shared memory.

Saves ~210k in the built intel drivers.

Bug: https://bugs.chromium.org/p/chromium/issues/detail?id=1048434
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5829>
 2020-07-17 17:44:17 +00:00
Eric Anholt
d4e56930c2 intel/perf: Fix unused var warning in release builds. 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5829>
 2020-07-17 17:44:17 +00:00
Eric Anholt
afe07c7fa7 intel: Fix release-build warnings about sf_entry_size. 
In one side of the ifdef it's only used in an assert.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5829>
 2020-07-17 17:44:17 +00:00
Anuj Phogat
559b26b7ee intel/ehl: Add new PCI-IDs 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
 2020-07-14 21:10:04 -07:00
Anuj Phogat
7cb2ace465 intel/ehl: Rename gen_device_info struct 
Renaming makes it easier to relate a pciid with device configuration.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
 2020-07-14 21:10:04 -07:00