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603 Commits

Author SHA1 Message Date
Qiang Yu c1cb168888 ac/llvm: remove redundant nir_lower_legacy_atomics 
Now both radeonsi and radv call it in driver.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23018>
 2023-05-16 04:10:32 +00:00
Qiang Yu 8cc7ad48d5 ac/llvm: remove the double frcp special handling 
KHR-GL45.gpu_shader_fp64.builtin.mod_* relaxed precision
requirement.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23012>
 2023-05-16 03:29:01 +00:00
Qiang Yu 521cbcb588 ac/llvm,radeonsi: enable lower_array_layer_round_even 
ACO need this to be done in nir. Remove the llvm round code
because both radv and radeonsi do this in nir for both aco
and llvm.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
 2023-05-15 02:01:11 +00:00
Qiang Yu 9bc1fb4c07 ac/llvm,radeonsi: lower nir_fpow for aco and llvm 
aco does not implement fpow, need nir to lower it
first. llvm will do by itself in the same way, so
we always lower fpow in nir now.

Remove the llvm fpow implementation that has special
handling for the muliplication. It's not used any
more and does not match GLSL spec as fpow(0,0)=NaN
but here we get 0.

There's some pixel changes for gl-radeonsi-stoney:
  ror-default 2 (no tolerance), 0 (1% tol.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
 2023-05-15 02:01:10 +00:00
Qiang Yu 19a8626f86 ac/llvm,radeonsi: lower some pack/unpack ops not supported by aco 
aco only support the split vertion of these instructions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
 2023-05-15 02:01:10 +00:00
Qiang Yu fb2d0fb4a2 ac/llvm,radeonsi: lower ineg in nir 
aco does not implement it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
 2023-05-15 02:01:10 +00:00
Qiang Yu 3fae161ff2 ac/llvm,radeonsi: lower txf offset in nir 
aco will complain if txf has offset. Not if other
texture ops.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
 2023-05-15 02:01:10 +00:00
Qiang Yu f13f9044db ac/llvm,radeonsi: lower fsin/fcos in nir 
ACO only support nir_fsin/cos_amd.

There's some pixel changes for gl-radeonsi-stoney trace.
Different pixels:
  furmark  61 (no tolerance), 0 (1% tol.)
  gimark   93867 (no tolerance), 888 (1% tol.)
  tessmark 39 (no tolerance), 0 (1% tol.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
 2023-05-15 02:01:10 +00:00
Qiang Yu f9d54b1d36 ac/llvm,radeonsi: lower idiv in nir 
aco does not implement these idiv ops.

nir_lower_idiv is for idiv ops <= 32bit and ported from
llvm amdgpu, so llvm do the same.

nir_lower_divmod64 is for 64bit idiv ops.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
 2023-05-15 02:01:10 +00:00
Marek Olšák f98871608c ac/llvm: rewrite and unify how GLC, DLC, SLC are set 
Use ACCESS_* flags in call sites instead of GLC/DLC/SLC.

ACCESS_* flags are extended to describe other aspects of memory instructions
like load/store/atomic/smem.

Then add a function that converts the access flags to GLC, DLC, SLC.

The new functions are also usable by ACO.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
 2023-05-12 21:45:44 +00:00
Marek Olšák 968db0208d ac/llvm: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT 
... and expect it to behave like ACCESS_NON_TEMPORAL.
Handling ACCESS_NON_TEMPORAL is sufficient.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
 2023-05-12 21:45:44 +00:00
Alyssa Rosenzweig 0241d8894e ac/llvm: Use unified atomics 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
 2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig 1e9c01523a ac/llvm: Don't handle atomic derefs 
Should not be seen, already would be stubbed out.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
 2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig 82430b91bb ac/llvm: Use nir_foreach_phi 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
 2023-05-12 14:02:23 +00:00
Timur Kristóf 9b6945bb65 amd: Cleanup old GS intrinsics code. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:59 +00:00
Timur Kristóf 009f0623ff ac/llvm: Clarify arguments of ac_build_sendmsg. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf 28d740fc0b amd: Move sendmsg defines to ac_shader_util. 
Will be used by ac/nir legacy and NGG lowerings.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf f66281c7fb amd: Add and implement gs_wave_id sysval. 
Contains a global wave ID of legacy GS waves.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf c1591bfc28 amd: Add and implement sendmsg_amd intrinsic. 
This intrinsic is going to be used for simplifying GS code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Marek Olšák 820c50ada3 nir: rename ACCESS_STREAM_CACHE_POLICY -> ACCESS_NON_TEMPORAL and document 
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22769>
 2023-05-04 01:55:22 +00:00
Qiang Yu a4b60295a7 aco,ac/llvm,radv,radeonsi: handle ps bc optimization in nir for radv 
The side effect is removing the aco/llvm backend bc optimization code
and linear/persp_centroid variable.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
 2023-04-26 03:27:26 +00:00
Qiang Yu 33d683bf09 ac/llvm: remove output variable declaration for radv ps 
radv ps does not support epilog when llvm, so outputs will always
be lowered to exports in nir.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
 2023-04-26 03:27:26 +00:00
Karol Herbst 9d7ba38013 ac/llvm: support shifts on 16 bit vec2 
In OpenCL we can actually end up with those.

Fixes `basic astype` and those `integer_ops` OpenCL CTS tests:
integer_hadd
integer_rhadd
integer_upsample
quick_short_shift
quick_ushort_shift

Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22597>
 2023-04-24 13:17:05 +02:00
Qiang Yu feeae0f18f ac/llvm,radeonsi: lower nir_load_point_coord_maybe_flipped in nir 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22523>
 2023-04-19 01:59:02 +00:00
Qiang Yu f7f0d31fcc nir,ac/llvm,radeonsi: replace nir_load_smem_buffer_amd with nir_load_ubo 
They use same instruction. Just because when the time
nir_load_smem_buffer_amd was introduced, radeonsi didn't support
pass buffer descriptor to nir_load_ubo directly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22523>
 2023-04-19 01:59:02 +00:00
Qiang Yu 75b75c6c0a ac/llvm,radeonsi: use texture non-uniform flag as waterfall switch 
Also for calling nir_lower_non_uniform_access() when ACO.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22523>
 2023-04-19 01:59:02 +00:00
Eric Engestrom 0a0e485421 amd: fix buggy usage of unreachable() 
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22529>
 2023-04-18 13:59:54 +00:00
Rhys Perry d291f368a0 ac/llvm: support implicit LOD for nir_texop_tg4 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22315>
 2023-04-18 10:42:07 +00:00
Qiang Yu cc891e871e ac/llvm,radeonsi: lower ps color load in nir 
Remove the color0/1 in ac_shader_abi which is used by
radeonsi only.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>
 2023-04-17 02:11:56 +00:00
Harri Nieminen f85f511a38 amd: fix typos in code 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22432>
 2023-04-13 23:08:22 +00:00
Harri Nieminen aea48a4ff1 amd: fix typos 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22432>
 2023-04-13 23:08:22 +00:00
Qiang Yu 45826e42c5 ac,aco: move gfx10 ngg prim count zero workaround to nir 
To simplify both llvm and aco backend and remove unnecessary
workaround code where prim count is known to be not zero.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22381>
 2023-04-13 08:12:03 +00:00
Timur Kristóf ba537ac25a ac/llvm: Cover runtime 0 in GFX10 gs_alloc_req workaround. 
Previously, the workaround only covered compile-time zero, but
this is insufficient and can cause GPU hangs in RadeonSI when
NGG culling is enabled.

Fix this by handling runtime zero in the workaround.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22370>
 2023-04-08 13:54:06 +00:00
Qiang Yu 2c78cbbfe1 ac/llvm: remove some unused code replaced by nir 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22304>
 2023-04-07 03:42:25 +00:00
Marek Olšák d3b03fedd8 amd: add initial code for gfx940 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
 2023-04-06 15:00:53 +00:00
Qiang Yu 7be81a680b ac/llvm: remove ac_build_opencoded_load_format 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu 1165758b8b ac/llvm,radeonsi: remove abi->load_inputs implementation 
No nir_load_input in VS now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu 531acf548a ac/llvm: move ac_fixup_ls_hs_input_vgprs to amd common 
To be shared with radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu 297f97a42b ac/llvm: vs_rel_patch_id can also be fixed up 
It's currently used when LS store output to LDS.
The LS/HS bug fix seems does not affect this case.
But we'd better treat it as other fixed args.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Marek Olšák e0d449dd40 amd: set the correct LLVM processor name for gfx1036 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22084>
 2023-03-29 20:36:09 +00:00
Marek Olšák 0b6a7cba0b amd: rename GFX1036 -> RAPHAEL_MENDOCINO 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22084>
 2023-03-29 20:36:09 +00:00
Qiang Yu 3df1c4455e ac/llvm: implement float16 nir_op_pack_(s|u)norm_2x16 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21552>
 2023-03-28 19:57:11 +00:00
Marek Olšák 5d8f0c570e amd/llvm: remove no-op code for vec3 loads in ac_build_tbuffer_load 
Formatted loads always support vec3, so this code didn't do anything.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22117>
 2023-03-27 22:38:07 +00:00
Marek Olšák 03c97b212e amd/llvm: fix handling of unsupported vec3 loads on gfx6 
VMEM loads promoted from vec3 to vec4 didn't trim the vector, thus
returning vec4 on gfx6 and vec3 on later generations, which callers
don't expect.

SMEM loads were adding an extra component on gfx6, causing same issues.

Fixes: 82919e2d - amd: lower subdword UBO loads in NIR
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8693

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22117>
 2023-03-27 22:38:07 +00:00
Qiang Yu 0cd89a27ed ac/llvm: add missing type convert for nir_load_buffer_amd 
Fixes: afcbccb078 ("ac/llvm: implement ACCESS_USE_FORMAT_AMD as buffer_load/store_format")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22043>
 2023-03-23 01:55:20 +00:00
Qiang Yu 5ddb46e963 ac/llvm: respect channel_type when ac_build_buffer_load 
Mainly for nir_load_smem_buffer_amd which pass i32 for this parameter.

Fixes: 8030fbcf16 ("nir,ac/llvm: add nir_load_smem_buffer_amd")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22043>
 2023-03-23 01:55:20 +00:00
Pierre-Eric Pelloux-Prayer 3f272fd15e ac/llvm: fix build with LLVM 17 
This builds with LLVM 12 -> 17 and a running a simple app seems to work.

I couldn't test LLVM 11 because meson fails with:

    Looking for a fallback subproject for the dependency llvm (modules:
    bitwriter, engine, mcdisassembler, mcjit, core, executionengine,
    scalaropts, transformutils, instcombine, amdgpu, bitreader, ipo, native)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8297
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22021>
 2023-03-21 15:05:25 +00:00
Qiang Yu 719366c2b2 ac/llvm,radeonsi: lower nir_load_ring_tess_factors_amd 
No one implement this intrinsic in llvm, so remove the
llvm entry too.

This will be used in TCS nir tess factor write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
 2023-03-16 04:33:30 +00:00
Timur Kristóf 819ba6f7ae ac/llvm: Remove unused function ac_build_struct_tbuffer_load. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16805>
 2023-03-15 14:54:28 +00:00
Timur Kristóf 22ca8c8561 ac/llvm: Implement typed buffer load intrinsic. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16805>
 2023-03-15 14:54:27 +00:00