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Author SHA1 Message Date
Lionel Landwerlin c5a42e4010 intel/fs: fix shader call lowering pass 
Now that we removed the intel intrinsic and just use the generic one,
we can skip it in the intel call lowering pass and just deal with it
in the intel rt intrinsic lowering.

v2: rewrite with nir_shader_instructions_pass() (Jason)

v3: handle everything in switch (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 423c47de99 ("nir: drop the btd_resume_intel intrinsic")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12113>
 2021-11-22 08:17:26 +00:00
Jesse Natalie 724a38eb94 CI/windows: Upload result.txt as an artifact 
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13893>
 2021-11-20 20:30:59 +00:00
Jesse Natalie 1e3db7923f CI/windows: Uprev piglit 
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13893>
 2021-11-20 20:30:59 +00:00
Alex Xu (Hello71) 60d95c5d0f Auto-enable TLSDESC support 
TLSDESC speeds up access to dynamic TLS. This is especially important
for non-glibc targets, but is also helpful for non-initial-exec TLS
variables.

The entry asm does not support TLSDESC, but it only accesses
initial-exec symbols, so it is not necessary to handle that separately.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12722>
 2021-11-20 11:57:40 -05:00
Alex Xu (Hello71) 8570a2a280 Use initial-exec TLS for glibc only, enable TLS elsewhere 
It is not portable to use initial-exec TLS in dlopened libraries. glibc
and FreeBSD allocate extra memory for extra initial-exec variables
specifically for libGL, but other libcs including musl do not.

Keep initial-exec disabled on FreeBSD since it is apparently broken for
some reason:

https://gitlab.freedesktop.org/mesa/mesa/-/issues/966#note_394512
https://github.com/jbeich/mesa/commit/81dbdb15d55054242eded0eb2f32621d583c1aaf

Enable TLS on OpenBSD and Haiku based on the u_thread.h comment that
emutls is better than pthread_getspecific, which seems plausible given
that emutls has strictly more information to work with.

Fixes #966.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12722>
 2021-11-20 11:56:34 -05:00
Ilia Mirkin df005c2a65 mesa: move around current texture object fetching 
We have to validate the target before fetching the current texture
object. Move this so that it happens later.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>
 2021-11-19 20:45:35 -05:00
Ilia Mirkin d814539c2b mesa: check target/format for Tex(ture)StorageMem* 
Noticed while doing an audit around _mesa_get_current_tex usage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>
 2021-11-19 20:45:13 -05:00
Mauro Rossi f659d00000 android: define cpp_rtti=false because libLLVM is built w/o RTTI 
libLLVM for Android is built without RTTI, but after commit ad86267
mesa inherits meson default RTTI enabled state

cpp_rtti=false is added to meson options in android/mesa3d_cross.mk

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13888>
 2021-11-20 02:25:12 +01:00
Marek Olšák cdeecadcb6 radeonsi: deduplicate min_esverts code in gfx10_ngg_calculate_subgroup_info 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 9d7ac70ffb radeonsi: implement shader culling in GS 
It already does compaction, so we just need to load vertex positions
and cull. This was easier than expected.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 492a61fe72 radeonsi: don't use ctx.stage outside of si_llvm_translate_nir 
si_llvm_translate_nir() changes ctx.stage, so the outside code shouldn't
use it. This hasn't caused any issues yet. Since ctx.stage starts as 0,
the first use in this commit was a tautology.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 1c5899900d radeonsi: simplify si_get_vs_key_outputs for GS 
ngg_culling is always 0 when GS is enabled. This will change in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák a368385b23 radeonsi: add is_gs parameter into si_vs_needs_prolog 
and disable the VS prolog code for GS.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák f96d1757bb radeonsi: restructure code that declares merged VS-GS and TES-GS SGPRs 
no change in the SGPR layout

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 2418da2d4a radeonsi: separate culling code from VS/TES (to be reused by GS) 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Nicholas Bishop 37c3e16d35 mesa/get: allow NV_pixel_buffer_object constants in GLES2 
The NV_pixel_buffer_object extension can be available in a GLES2
context, so the PIXEL_PACK_BUFFER_BINDING/PIXEL_UNPACK_BUFFER_BINDING
constants should also be available.

Tested on 8086:2e12, "Mesa DRI Intel(R) Q45/Q43 (ELK)".

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5655
Signed-off-by: Nicholas Bishop <nicholasbishop@google.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13862>
 2021-11-19 23:21:52 +00:00
Jesse Natalie b8f41c5c4e d3d12: Validate opened D3D12 resource matches pipe template 
Unlike Linux dma-bufs, D3D12 resources are strongly typed, and
can't necessarily just reinterpret the memory arbitrarily.

Allow importing resources with no description coming from the frontend,
and populate the resource desc from the driver instead. If there was
a template, make sure that it matches the incoming resource.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 9740141b2e d3d12: Generate a pipe format -> typeless mapping table too 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie ca7d4fcb3f d3d12: Generate format table using a macro list 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 25bcc56027 d3d12: Make format list all use macros 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 96012b686e d3d12: Handle import/export of fd shared handles 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 31c7a04b47 winsys/d3d12: Populate winsys handle format 
All other winsys handle users do so, and a future commit will
start caring about it.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 2771fd4a3f gallium, windows: Use HANDLE instead of FD for external objects 
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 5bfbf4bec9 microsoft/compiler: Handle GLES external textures 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 2188607014 d3d12: Support RGBX formats mapped to RGBA 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie ab9948997a d3d12: Support PIPE_CAP_MIXED_COLOR_DEPTH_BITS 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie e0576ec148 d3d12: Support BGRA 555 and 565 formats 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie d0bc4974fa android: Allow forcing softpipe 
When dealing with swrast, there's two possibilities: If you have LLVM, you get
llvmpipe, which is pretty fast. If you don't, you get softpipe, which is slow,
but does have a couple nice qualities, like being smaller and not needing
executable memory for JIT.

If you're building a driver that requires LLVM like radeonsi then you need the
LLVM stub for the build to find LLVM. But for swrast, since it can mean either
softpipe/llvmpipe, you don't strictly need LLVM. So this just makes the
Android build files flexible like the Meson build files (where you can specify
-Dllvm=disabled even if LLVM is findable).

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
 2021-11-19 21:21:35 +00:00
Jesse Natalie 33e5a4378e android,d3d12: Support using DirectX-Headers dependency from AOSP 
Note that the Android build system apparently lowercases stuff,
so add a lowercase "directx-headers" dependency which is searched first,
before falling back to the proper-cased "DirectX-Headers" dependency.

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
 2021-11-19 21:21:35 +00:00
Jesse Natalie 6138b047e2 mesa/main, android: Log errors to logcat 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
 2021-11-19 21:21:35 +00:00
Jesse Natalie 9e82a56745 android: Add a BOARD CFlags option so build can be customized 
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
 2021-11-19 21:21:35 +00:00
Mike Blumenkrantz 81cc94b8f0 zink: be consistent about waiting on context queue on context destroy 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>
 2021-11-19 18:56:10 +00:00
Mike Blumenkrantz e92b8956c7 zink: set batch state queue on creation 
make this easier to find

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>
 2021-11-19 18:56:10 +00:00
Emma Anholt b8ffd7a888 freedreno/a5xx: Emit MSAA state for sysmem rendering, too. 
This looked obviously wrong, we want to set the sample counts for sysmem
too just like we do on 6xx.  Turns out it fixes some piglits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
 2021-11-19 17:24:11 +00:00
Emma Anholt 5071d39cb2 freedreno/a5xx: Document the sRGB bit on RB_2D_SRC/DST info. 
Noticed while looking through my set of traces for where the average bit
might be.  Same spot as on a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
 2021-11-19 17:24:11 +00:00
Emma Anholt 1ef6465665 freedreno/a5xx: Define a5xx_2d_surf_info like a6xx has. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
 2021-11-19 17:24:11 +00:00
Emma Anholt cad0b6e2e5 freedreno/a6xx: Disable sample averaging on non-ubwc z24s8 MSAA blits. 
The fallback path we averages unorm textures, but if we don't have ubwc on
either then we can just cast them to uint which then just takes sample 0.

The proper UBWC format I think ends up averaging, though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
 2021-11-19 17:24:11 +00:00
Emma Anholt 93eb697a8d freedreno/a6xx: Disable sample averaging on z/s or integer blits. 
We can't generally force fd_blitter_blit() to not average in our fallback
blits, but this should at help some cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
 2021-11-19 17:24:11 +00:00
Connor Abbott c98adc56f4 ir3/lower_pcopy: Fix bug with "illegal" copies and swaps 
If the source and destination were within the same full register, like
hr90.x and hr90.y (which both map to r45.x), then we'd perform the
swap/copy with the wrong register. This broke
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35 once BDA is enabled.

Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
 2021-11-19 16:59:54 +00:00
Connor Abbott 65da866ad9 ir3/lower_pcopy: Fix shr.b illegal copy lowering 
The immediate shouldn't be half-reg because the other source isn't.
Fixes an assertion failure with
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35.

Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
 2021-11-19 16:59:54 +00:00
Connor Abbott 9912c61362 ir3/spill: Support larger spill slot offset 
This is required by
dEQP-VK.ssbo.phys.layout.random.all_shared_buffer.47, where we need to
spill a lot of pointers due to NIR CSE being a little too aggressive and
creating a large register pressure across basic blocks, too large to fit
within the boundaries of ldp/stp offsets.

Note that this will be a lot more difficult with support for "real
functions" because the base register will become unknown at compile
time. However this hack gets things working for the time being.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
 2021-11-19 16:59:54 +00:00
Connor Abbott 29d3889bbb ir3/ra: Add missing asserts to ra_push_interval() 
This would've caught the previous issue earlier. We checked that the
physreg made sense when inserting via ra_file_insert() but not
ra_push_interval() which is used for live-range splitting.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
 2021-11-19 16:59:54 +00:00
Connor Abbott 9d88b98b08 ir3/ra: Consider reg file size when swapping killed sources 
Don't swap a 2-component vector of half-regs with a full reg if that
would result in the half regs going outside of the allowable half-reg
space.

Fixes: d4b5d2a020 ("ir3/ra: Use killed sources in register eviction")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
 2021-11-19 16:59:54 +00:00
Jesse Natalie f9a46ad22a meson: Allow mismatching RTTI for MSVC 
This might be safe to relax to all Windows compilers, but I didn't
test Clang or MinGW, so scoping to MSVC for now. For MSVC, this is
safe to mismatch, because the vftables are emitted into all objects
with "pick largest," and the definition with RTTI is larger than the
one without. This is different than the Itanium ABI, which only emits
one copy of the typeinfo in the object which defines the key method.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13064>
 2021-11-19 15:36:59 +00:00
Jesse Natalie ad86267412 meson: Don't override built-in cpp_rtti option, error if it's invalid 
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13064>
 2021-11-19 15:36:59 +00:00
Lionel Landwerlin 21ec880bf9 anv: initialize anv_bo_sync base fields 
v2: zalloc

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cbb13fae33 ("anv: Add a BO sync type")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13875>
 2021-11-19 15:09:43 +00:00
Lionel Landwerlin 04bd5bb69b anv: don't try to close fd = -1 
CID: 1464334

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13879>
 2021-11-19 14:52:29 +00:00
Samuel Pitoiset ddbc84d5a0 radv: ignore the descriptor set layout when creating descriptor template 
From the Vulkan spec:
    "This parameter is ignored if templateType is not
     VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET."

This fixes an assertion about the base object type when running Yuzu
with Vulkan validation layers enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13846>
 2021-11-19 13:52:36 +00:00
Samuel Pitoiset 2436cafffe radv: allow TC-compat CMASK with storage images on GFX10+ 
Hardware seems to support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12173>
 2021-11-19 13:30:40 +00:00
Mike Blumenkrantz 22d9d0f8b5 zink: add a compiler pass to scan for shader image use 
other frontends and internal shaders won't set this

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13864>
 2021-11-19 13:14:46 +00:00