Commit Graph

14514 Commits

Author SHA1 Message Date
Caio Oliveira c19a4150b5 intel/brw: Simplify variant tracking in brw_compile_fs
Remove the cfg variables and use the shader pointers directly.  Reset
the variant pointer if a shader failed or will not be used.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>
2025-08-28 00:06:20 +00:00
Caio Oliveira 834e30d244 intel/brw: Simplify tracking of dispatch_width_limit in brw_compile_fs
Keep it in a variable, that way don't need to check which shader to look
for the limit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>
2025-08-28 00:06:20 +00:00
Caio Oliveira 9d53e27579 intel/brw: Remove brw_shader::import_uniforms()
The brw_shader::uniforms now is derived from the nir_shader.  The
only exception is compute shaders for older Gfx versions, so we
move the adjust logic for that.

The benefit here is untangling the code for compilation variants,
that before needed to keep track of the first that compiled to,
in most cases, copy an integer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>
2025-08-28 00:06:19 +00:00
Caio Oliveira 0b4d62d340 anv: Allocate prog_data->param array when making internal kernels
As we set prog_data->nr_params, allocate the array like elsewhere.
Current code is getting by because the logic for adding a new element
will realloc it.  But later changes will make the array be accessed
before this reallocation.

This will make sure later patches won't cause tests like

  dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary

to fail in gfxver < 125.  Note the bug appears when DRI option
to tweak the thresold to use these shaders is set to 0.  This is
done by the GitLab CI, which allowed testing later patches to find
this issue.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>
2025-08-28 00:06:19 +00:00
Caio Oliveira b8a35a8a27 brw: Pass per_primitive_offset in brw_shader_params
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>
2025-08-28 00:06:19 +00:00
Caio Oliveira 6ca9021758 brw: Add brw_shader_params
And unify the initialization code for brw_shader.  Avoid passing
brw_compile_params since for a single compilation we might have
multiple shaders (the case for BS stage).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>
2025-08-28 00:06:18 +00:00
Caio Oliveira 1c933b6511 brw: Fix checking sources of wrong instruction in opt_address_reg_load
Fixes: 8ac7802ac8 ("brw: move final send lowering up into the IR")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37019>
2025-08-27 22:50:23 +00:00
Lionel Landwerlin 93996c07e2 brw: fix broadcast opcode
The problem with the current code is that there is a disconnect between :
   - the virtual register size allocated
   - the dispatch size
   - the size_written value

Only the last 2 are in sync and this confuses the spiller that only
looks at the destination register allocation & dispatch size to figure
out how much to spill.

The solution in this change is to make BROADCAST more like
MOV_INDIRECT, so that you can do a BROADCAST(8) that actually reads a
SIMD32 register. We put the size of the register read into src2.

Now the spiller sees correct read/write sizes just looking at the
destination register & dispatch size.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 662339a2ff ("brw/build: Use SIMD8 temporaries in emit_uniformize")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13614
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36564>
2025-08-28 00:23:44 +03:00
Lionel Landwerlin e6ca709a4e brw: fix INTEL_DEBUG=spill_fs
We need to dirty the instruction BRW_DEPENDENCY_INSTRUCTIONS &
BRW_DEPENDENCY_VARIABLES if anything was spilled.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a6b0783375 ("brw: Use brw_ip_ranges in scheduling / regalloc")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13233
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36925>
2025-08-27 15:08:35 +00:00
Tapani Pälli ad2ef16198 iris/anv: toggle on CACHE_MODE_0::MsaaFastClearEnabled on BMG G31
This increases rate of depth fast clear rate on BMG G31
per HSD 22020044224.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966>
2025-08-26 19:35:34 +00:00
Tapani Pälli c65f5cd36d intel/dev: provide a helper to detect bmg g31 device
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966>
2025-08-26 19:35:33 +00:00
Tapani Pälli 2c9bc313a0 intel/genxml: update CACHE_MODE_0 register for gfx200
Field that we currently utilize does not change place, however
there are some new fields so let's update contents to match spec.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966>
2025-08-26 19:35:33 +00:00
Lionel Landwerlin 3362b8dcb5 brw: use a scalar builder for the load_payload on transpose loads
I noticed SIMD32 shaders have that kind of pattern :

mov(32)         g94<1>D         0D                              { align1 WE_all };
send(1)         g15UD           g94UD           nullUD          0x6210d500                0x02010000
                ugm MsgDesc: ( load, a32, d32, V16, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti )  BTI 2  base_offset 16  { align1 WE_all 1N I@5 $1 };

Why use a 32 wide register for a SEND that is only going to read the first lane?

We can stick a single physical register and reduce register pressure.

DG2 fossils-db results :

Totals:
Instrs: 157417515 -> 157417796 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15362185116 -> 15363086774 (+0.01%); split: -0.05%, +0.05%
Max live registers: 29059141 -> 29051166 (-0.03%)
Max dispatch width: 5071256 -> 5075720 (+0.09%); split: +0.33%, -0.24%

Totals from 82132 (14.43% of 569221) affected shaders:
Instrs: 26564632 -> 26564913 (+0.00%); split: -0.00%, +0.00%
Cycle count: 4630907475 -> 4631809133 (+0.02%); split: -0.16%, +0.18%
Max live registers: 5425037 -> 5417062 (-0.15%)
Max dispatch width: 128384 -> 132848 (+3.48%); split: +12.92%, -9.45%

LNL fossils-db results :

Totals:
Instrs: 141870413 -> 141870745 (+0.00%); split: -0.00%, +0.00%
Cycle count: 20176018818 -> 20191262632 (+0.08%); split: -0.07%, +0.14%
Max live registers: 44858167 -> 44838370 (-0.04%)

Totals from 51859 (10.55% of 491590) affected shaders:
Instrs: 16834547 -> 16834879 (+0.00%); split: -0.00%, +0.00%
Cycle count: 5761980106 -> 5777223920 (+0.26%); split: -0.24%, +0.50%
Max live registers: 5893878 -> 5874081 (-0.34%)

Perf A/B testing only reported a 0.5% improvement on DG2 on one trace, no changes on BMG.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36958>
2025-08-26 12:03:22 +00:00
Lionel Landwerlin 27c69acb6a brw: remove uniform from opt_offsets
Those are for push constants, no point in doing that because :
   - there is no HW constant offsets in push constants (payload
     delivery), it's just register offset calculation
   - if we have an dynamic value it's already using MOV_INDIRECT

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e103afe7be ("brw: run the nir_opt_offsets pass and set the maximum offset size")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36958>
2025-08-26 12:03:22 +00:00
Sagar Ghuge 2cd564c1de anv: Add missing L3 flushes
We are reading out some of the parameters from IR data structure those
have been written previously, on some platforms L3 is not coherent, so
explicitly add those flushes.

Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36952>
2025-08-25 17:36:08 +00:00
Sagar Ghuge 4473e21e2f anv: Enable CS stall for ACCELERATION_STRUCTURE_COPY stage
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36952>
2025-08-25 17:36:08 +00:00
Sagar Ghuge 75d770b4f8 anv: Add missing ACCELERATION_STRUCTURE_READ in barrier handling
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36952>
2025-08-25 17:36:08 +00:00
Eric Engestrom fa74e939bf ci/piglit: automatically use LAVA proxy
This avoids having to hardcode the proxy in the traces `download-url` or
jobs setting `PIGLIT_REPLAY_EXTRA_ARGS` and accidentally overriding the
default args when the author meant to append.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36955>
2025-08-25 14:52:38 +00:00
Konstantin Seurer 9df7b48d2f nir: Use nir_def_as_* in more places
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36746>
2025-08-24 14:03:09 +00:00
Yiwei Zhang dcffe932a0 anv: adopt common GetAndroidHardwareBufferPropertiesANDROID
ANV currently carries a partial copy of the gralloc mapper's format
resolving code, while the ground truth solely resides inside the
gralloc. The local copy is delicate and unable to maintain compatibility
with different gralloc implementations because AHB formats like
Y8Cb8Cr8_420 and IMPLEMENTATION_DEFINED are flexible formats, and can be
resolved to different underlying drm fourcc formats depending on the
usage and media IPs.

The common impl is more correct as it relies on the info from gralloc
mapper side, and it only sets the minimal set of explicit formats to
avoid hitting spec corner case of allocating out AHB with flexible
formats (missing half of the media usage bits might end up allocating
something different that potentially get resolved to a different
VkFormat as well).

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36866>
2025-08-22 23:40:35 +00:00
Yiwei Zhang a34eb09c89 anv: drop anv_ahb_format_for_vk_format
The vk_image::ahb_format is for drivers that support more than the
common explicit AHB formats. It is used on AHB image memory export
allocation path, and more specifically vk_device_memory_create will
use that AHB format to allocate the AHB out from gralloc. To be noted,
export allocation path only deals with explicit format but not external
format. So even with the obsolete HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL
private format, we don't need such either as multi-planar formats are
supposed to be reported as external format.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36866>
2025-08-22 23:40:35 +00:00
Yiwei Zhang ef885eb9ac anv: adopt vk_android_get_ahb_image_properties
The current impl misses the probe against gralloc mapper, which is the
required handshake before advertising support. For simplicity, just
adopt the common AHB helper. It does not rely on driver specific format
mapping, since the query doesn't allow external format at all.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36866>
2025-08-22 23:40:34 +00:00
Yiwei Zhang 3b19aa6261 anv: avoid setting image format twice for AHB image
AHB images are created with the right VkFormat when external format
isn't used. When external format does get used, the proper VkFormat has
already being set in the common runtime. Upon AHB props query, we
resolve external format to VkFormat and set to the externalFormat field
to be used by the app. The app would than chain the exact external
format when creating the AHB image if it wants to go down the external
format code path instead of being explicit. So in the end, the format we
resolve is the format we get. Thus no need to set it twice.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36866>
2025-08-22 23:40:34 +00:00
Yiwei Zhang b6427520d6 anv: drop obsolete anv_create_ahw_memory
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36866>
2025-08-22 23:40:33 +00:00
Lucas Fryzek b927b52e24 hasvk: Remove special CROS_GRALLOC path from format logic
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36866>
2025-08-22 23:40:32 +00:00
Lucas Fryzek a43fa85fab anv: Remove special CROS_GRALLOC path from format logic
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36866>
2025-08-22 23:40:32 +00:00
Faith Ekstrand 59f85e678f vulkan/wsi: Take a vk_queue in wsi_common_queue_present()
The common entrypoint wrapper already depends on vk_queue, as do all the
drivers that implement drv_QueuePresentKHR() so there's no point in
passing through Vulkan API types anymore.

The one functional change here is that ANV is no longer forcing the
queue index to be zero, which I suspect was a mistake in the first
place.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36827>
2025-08-22 23:05:02 +00:00
Faith Ekstrand 81325cf887 vulkan,anv,hasvk: Drop vk_queue_wait_before_present()
This helper existed to ensure that drivers waited for semaphores to
materialize before processing a QueuePresent().  However, most drivers
never called this and they were kind-of fine.  Now that we have explicit
and dma-buf sync built into WSI, this wait happens as part
GetSemaphoreFd when we fetch the sync file from the semaphore.

It's also less racy to just rely on GetSemaphoreFd() because, even
though we were stalling the submit thread prior to present, the present
itself does one or more submits and those may go to the thread and
potentially race with the window system.  The GetSemaphoreFd(), however,
happens at the right time to ensure we actually stall before handing
off to the window system.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36827>
2025-08-22 23:05:02 +00:00
Faith Ekstrand 650debdf40 anv: Stop picking our own blit queue
This reverts commit 1f0fdcb619 ("anv: always pick graphics queue to
execute prime blits on.") which was added to avoid prime blits on video
queues.  However, this was fixed properly in d7938de8fe ("vulkan/wsi:
don't support present with queues where blit is unsupported") which
made us stop advertising presentation on video queues entirely.  We no
longer need the code in ANV.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36827>
2025-08-22 23:05:01 +00:00
Faith Ekstrand e0c30b0fc2 anv,hasvk: Use vk_drm_syncobj_copy_payloads
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36827>
2025-08-22 23:05:00 +00:00
Collabora's Gfx CI Team 640e2eddea Uprev ANGLE to 995c4c4d89ed6a5c28b210e9c0f83eb4f8b6e2f5
https://github.com/google/angle/compare/6a04a50f98cac71b25464d10289ce7a013841caf...995c4c4d89ed6a5c28b210e9c0f83eb4f8b6e2f5

- Skip tests failing on all drivers due to a CTS bug
- Disable clang options not supported by the 'unbundled' toolchain

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36908>
2025-08-22 07:35:15 +00:00
Iván Briano 07057e270c anv, hasvk: allow using a 3D image as a resolve target
This is allowed by the specification, as the following VUIDs state:

   VUID-vkCmdResolveImage-srcImage-04446
   If dstImage is of type VK_IMAGE_TYPE_3D, then for each element of
   pRegions, srcSubresource.layerCount must be 1

   VUID-vkCmdResolveImage-srcImage-04447
   If dstImage is of type VK_IMAGE_TYPE_3D, then for each element of
   pRegions, dstSubresource.baseArrayLayer must be 0 and
   dstSubresource.layerCount must be 1

New tests coming for it: dEQP-VK.pipeline.*.multisample.3d.*

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36895>
2025-08-21 20:53:42 +00:00
Caio Oliveira 74a4e7dd4b brw: Fix folding case for MAD instruction with all immediates
Fixes: b605f76b2a ("brw/algebraic: Constant fold multiplicands of MAD")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36867>
2025-08-21 17:19:18 +00:00
Caio Oliveira eec64c865f brw: Add disabled test for MAD constant folding
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36867>
2025-08-21 17:19:18 +00:00
Lionel Landwerlin 1bab95551a anv: fix uninitialized return value
We don't go through the loop when there are no queues.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 884df891d7 ("anv: allow device creation with no queue")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36910>
2025-08-21 16:07:56 +00:00
Calder Young c7e48f79b7 brw,anv: Reduce UBO robustness size alignment to 16 bytes
Instead of being encoded as a contiguous 64-bit mask of individual registers,
the robustness information is now encoded as a vector of up to 4 bytes that
represent the limits of each of the pushed UBO ranges in 16 byte units.
Some buggy Direct3D workloads are known to depend on a robustness alignment
as low as 16 bytes to work properly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36455>
2025-08-21 09:04:55 +00:00
Lionel Landwerlin 2281e88381 brw: make assign_curb_setup visible in optimizer debug
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36455>
2025-08-21 09:04:54 +00:00
Lionel Landwerlin df37c7ca74 brw: fix analysis dirtying with pulled constants
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5c17299084 ("brw: enable A64 pulling of push constants")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36455>
2025-08-21 09:04:53 +00:00
Yiwei Zhang fc2c490975 anv: advertise present_id/wait behind ANV_USE_WSI_PLATFORM
wsi_common_vk_instance_supports_present_wait returns true for all
supported wsi platforms here, so we can unconditionally advertise them
behind ANV_USE_WSI_PLATFORM like the other wsi extensions (also to not
tangle with Android).

v2: guard presentId2 and presentWait2 features as well

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Acked-by: Daniel Stone <daniels@collabora.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36835>
2025-08-21 07:53:15 +00:00
Yiwei Zhang 9669b1852b hasvk: advertise present_id/wait behind ANV_USE_WSI_PLATFORM
wsi_common_vk_instance_supports_present_wait returns true for all
supported wsi platforms here, so we can unconditionally advertise them
behind ANV_USE_WSI_PLATFORM like the other wsi extensions (also to not
tangle with Android).

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36835>
2025-08-21 07:53:15 +00:00
Valentine Burley 7ea1da4af4 iris/ci: Add a new iris deqp job on Alder Lake
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36880>
2025-08-21 07:05:27 +00:00
Valentine Burley e0220c6e71 anv/ci: Add a job replaying traces with ANGLE
The new anv-adl-traces-restricted job runs 10 ANGLE traces on Alder Lake,
using ANGLE's Vulkan backend.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36880>
2025-08-21 07:05:27 +00:00
Valentine Burley 1fce16d33f anv/ci: Run full anv-adl-angle job pre-merge
We have enough devices to run the full job without a fraction, which also
allows deleting the nightly job.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36880>
2025-08-21 07:05:26 +00:00
Marek Olšák c601308615 nir: convert nir_instr_worklist to init/fini semantics w/out allocation
This removes the malloc overhead.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36728>
2025-08-21 06:13:49 +00:00
Marek Olšák 3aadae22ad nir: make nir_block::predecessors & dom_frontier sets non-malloc'd
We can just place the set structures inside nir_block.

This reduces the number of ralloc calls by 6.7% when compiling Heaven
shaders with radeonsi+ACO using a release build (i.e. not including
nir_validate set allocations, which are also removed).

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36728>
2025-08-21 06:13:48 +00:00
Iván Briano 20f546d6c1 anv: fix capture/replay of sparse images with descriptor buffer
We were not implementing vkGetImageOpaqueCaptureDescriptorDataEXT,
relying on the common implementation that does nothing. That works well
enough for regular images because the fixed address needed for
capture/replay is handled by the memory allocation path, but for sparse
images we initialize the sparse bindings at image creation time.

Here we implement the function to retrieve the addresses of all the
used bindings for the image, then use all of them at creation time.
Also, set the correct alloc_flags for this to work.

Fixes: 43b57ee8a5 ("anv: add capture/replay support for image with descriptor buffers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35872>
2025-08-20 21:08:10 +00:00
Nataraj Deshpande f67edacf8b anv: add feature flags for linearly tiled ASTC images
In case of emulated ASTC on supported platforms, currently returning
0 for linear tiled images causes vpGetPhysicalDeviceProfileSupport
failure during AndroidBaselineProfile test. The patch handles it
similar to linearly-tiled images that are used for transfers.

Fixes android.graphics.cts.VulkanFeaturesTest#testAndroidBaselineProfile2021Support.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36798>
2025-08-20 15:28:50 +00:00
Lionel Landwerlin fe38fb858c brw: workaround broken indirect RT messages on Gfx11
Unfortunately we cannot use the indirect descriptor on Gfx11, it
appears to just drop writes. Other platforms appear to be fine.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36883>
2025-08-20 15:01:50 +00:00
Lionel Landwerlin a0844458b8 brw: enable opt_register_coalesce to work with multiple EOT blocks
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36883>
2025-08-20 15:01:50 +00:00
Lionel Landwerlin c4c7ff3f8f brw: enable register allocation to deal with multiple EOTs
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36883>
2025-08-20 15:01:50 +00:00