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Erik Faye-Lund b7601dd27e zink: wrap discard in a function 
This makes discard less weird, and allows us to treat it as
control-flow. This makes things less bizarre for drivers.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7070
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
 2022-08-26 10:05:03 +00:00
Erik Faye-Lund 47d67912bd zink: add spirv_builder_function_call 
It can be useful not just to create functions, but also being able to
call them. This adds the spirv_builder-helper for this.

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
 2022-08-26 10:05:03 +00:00
Erik Faye-Lund 41dfed6e12 zink: type_main -> type_void_func 
This type will be reused later on, so let's have the name describe what
is *is*, not what it's *used for*.

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
 2022-08-26 10:05:03 +00:00
Jordan Justen f4c44444ad intel/pci_ids: Add 0x468b ADL-S PCI-id 
Ref: bspec 53655
Fixes: d399c3e861 ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
 2022-08-26 08:50:42 +00:00
Jordan Justen 6ca37aabfb intel/pci_ids: Update ADL-S strings 
Ref: bspec 53655
Fixes: d399c3e861 ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
 2022-08-26 08:50:42 +00:00
Gert Wollny bf4234d088 r600/sfn: Use a low number for unused target register 
This reduces the number of registers reserved by the shader
units and makes more threads possible.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6856

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
 2022-08-26 08:27:42 +00:00
Gert Wollny 90f99369ae r600: Fix reporting TGSI IR support 
When NIR is not explicitely enabled we still support TGSI.

Fixes: 33765aa92a
    r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
 2022-08-26 08:27:42 +00:00
Gert Wollny c81fe5b235 r600/sfn: Use a heuristic to keep SSBO setup and store close 
When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

v2: do handling in shader block to be thread save (hinted to by Filip)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
 2022-08-26 08:27:42 +00:00
Gert Wollny 1f5dccb760 r600/sfn: Don't scan the whole block for ready instructions 
Limit the number of tested instructions and the number of
ready instructions that might be taken into account.

This reduces the time needed to run the scheduler significantly.

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
 2022-08-26 08:27:42 +00:00
Gert Wollny 79eabb8130 r600/sfn: Don't schedule GDS instructions early 
Atomic GDS instructions like inc, dec, or read will increase the
register pressure, therefore we shouldn't prioritize scheduling them.

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Fixes: 79ca456b48
    r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
 2022-08-26 08:27:41 +00:00
Gert Wollny fd71cd0b6a r600/sfn: Don't tag mem-ring and stream instructions as exports 
Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.

When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.

This fixes
  spec@glsl-1.50@execution@variable-indexing@gs-output-array-vec4-index-wr

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
 2022-08-26 08:27:41 +00:00
Gert Wollny 3a0f085837 r600/sfn: Handle color0 writes all on R700 like on EG 
Fixes: 069f3869ac
    r600/sfn: Fix color outputs when color0 writes all

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
 2022-08-26 08:27:41 +00:00
Lucas Stach 43eb5e777e etnaviv: add debug option to disable linear PE feature 
Linear PE has already shown to have some rough corner cases in the hardware
and also has performance implications. Add a debug option to allow to disable
the feature, so users can more easily check if some issue is caused by this
feature.

CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
 2022-08-26 07:47:09 +00:00
Lucas Stach ea8fc9592c etnaviv: use linear PE rendering only on properly aligned surfaces 
When linear rendering is used together with TS, the color tiles must be fully
contained in a single row of pixels. When wrapping around to the next row
TS gets confused and records wrong tile status information, leading to visual
corruption when the surface is resolved/decompressed.

The corruption can be fixed by increasing the stride alignment for linear
render targets, but that would break some existing use-cases, as some display
engines used together with Vivante GPUs currently don't support strides that
don't match the horizontal display resolution.

For now only enable linear PE rendering when the surface is properly aligned
already. This allows to use the optimization in a lot of common use-cases, but
falls back to the proven tiled rendering with subsequent resolve into linear
for the problematic cases.

CC: mesa-stable #22.2
Fixes: 53445284a4 ("etnaviv: add linear PE support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
 2022-08-26 07:47:09 +00:00
Lucas Stach 09953d7b75 etnaviv: move checking for MC2.0 for TS into screen init 
The decision whether to use fast clear aka TS currently checks for two
feature bits: FAST_CEAR and MC20. We check for MC20, as TS on MC1.0 bypasses
the memory offset and we don't have any way to fixup the GPU address to
account for that. It could be done with some support of the kernel driver,
but then GPUs with MC1.0 are very rare to find these days, so not sure if we
are ever going to bother with that.

Instead of checking two separate feature bits to determine if TS can be used,
mask out the FAST_CLEAR bit from the features when MC20 isn't present. This
way we only have to check for a single feature bit.

CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
 2022-08-26 07:47:09 +00:00
Samuel Pitoiset 68e69d002f radv: stop emitting RMW context registers for updating sample locations 
RMW context registers have been removed in RadeonSI a while ago
because they don't seem good for performance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
 2022-08-26 06:33:05 +00:00
Samuel Pitoiset 2f5891108a radv: cleanup dynamic states in radv_emit_graphics_pipeline() 
Some dynamic states always need to be emitted when the first pipeline
is emitted, some others depend on pipeline state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
 2022-08-26 06:33:05 +00:00
Samuel Pitoiset 85a55009be radv: stop clearing bitfields for registers that are emitted dynamically 
These fields aren't set at pipeline creation, so clearing them is
just useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
 2022-08-26 06:33:05 +00:00
Samuel Pitoiset 7aaa016b23 radv: stop setting CB_COLOR_CONTROL.ROP3 from the pipeline 
This is useless because logic op is a dynamic state and it's already
emitted from the cmdbuf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
 2022-08-26 06:33:05 +00:00
Qiang Yu b5c10a9028 ac/llvm: cast tes_u/v_replaced to float 
Otherwise LLVM float ops fail to operate on them.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu f75452918b ac/nir/ngg: support clipdist culling 
Port from radeonsi.

Besides vertex position based primitive culling, clipdist
attribute can also be used to cull a primitive. Normally
it's used by fixed-pipeline, but when NGG we can treate it
as a culling condition to filter out invisible primitive
before fixed-pipeline.

There are two kinds of clipdist:
1. user define a clip plane explicitly by glClipPlane(),
   fixed-pipeline calculate with vertex position to get
   clipdist, then cull. This is the legacy way.
2. Now GLSL define gl_ClipDistance/gl_CullDiatance so that
   user can calculate clipdist in any way he like.

This implementation support both way.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu 620e62bb39 ac/nir/ngg: support component position store 
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu 1bdeb961bd ac/nir/ngg: add gs culling 
Port from radeonsi.

Cull primitive after GS thread and before final vertex/primitive
export. GS culling is like VS/TES culling which read out saved
vertex positions of a primitive from LDS then call the primitive
culling algorithm to check whether it's visiable or not, only
passed primitives will be exported.

Unlike the VS/TES culling that read vertex index of a primitive
from VGPRs as shader args, GS will set a primitive complete flag
for each last vertex of a primitive in LDS, so that vertex thread
know the previous 1/2/3 vertex can form a primitive and do primitive
culling.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu b212fd4b1e ac/nir/ngg: save and restore position output base for nogs 
radeonsi has different driver_location and io location.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu 7e17e01973 ac/nir/ngg: save and restore output bit size for gs 
radeonsi does not have io nir variables, so need to save output
bit size when lower store_output intrinsic.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu 93a635c2c8 ac/nir/ngg: use same driver location for gs output 
driver_location and io location are different for radeonsi,
and radeonsi llvm rely on the correct driver_location to
index output variables.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu 347a94666c ac/nir/ngg: fix and simplify gs store output lower 
Simplify: 64bit IO has been lowered by nir_lower_io with
nir_lower_io_lower_64bit_to_32, so no need to handle in the
ngg lower.

Fix: we need to increase io_sem.location by base_offset for
correct gs_output_info.

radeonsi has different driver_location and io location, so
also change the output variable index to io location.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu db0e9d3cab ac/nir/ngg: support line culling 
Port from ac_llvm_cull.c

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu f1f2c931a7 ac/nir/cull: support caller react when primitive is rejected 
Make accept_func optional, and return accpect result for caller
react when primitive is rejected.

This is for GS culling.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu 035d70f721 ac/nir/ngg,radv: use nir_load_viewport_xy_scale_and_offset 
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu a19dcdf9d5 nir,ac/llvm: add nir_intrinsic_load_viewport_xy_scale_and_offset 
Used by RADV/Radeonsi NGG culling. Pack them into a single vec4
load for radeonsi to reduce const buffer load.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu 1aef9c8318 nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd 
Used by AMD GPU NGG line culling. We could use nir load
line width and viewport scale to calculate this in shader,
but this way needs expensive divide ops.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Dave Airlie 0c2b824f67 gallivm: don't indirect image/sampler destroy. 
These are pointless indirections, just call direct the destroy
functions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
 2022-08-26 04:39:59 +00:00
Dave Airlie 5fdd77c7f2 gallivm/sample: remove unused base parameter from dynamic callbacks. 
This parameters was never used anywhere, so just remove it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
 2022-08-26 04:39:59 +00:00
Dave Airlie 1f0d1a96cb gallivm: drop unused parameter to lp_build_sample_aos 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17946>
 2022-08-26 04:39:59 +00:00
Emma Anholt bc2e1a3ed6 ci: disable the freedreno farm. 
It seems to have gone down at the end of the day today.  I'm off tomorrow,
someone else can debug.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18263>
 2022-08-26 04:02:15 +00:00
Emma Anholt 6b338d6cc5 ci: Move 'never' rules includes above "on_success" rules includes. 
The farm online-ness filters were listed after some of the checks for
whether code changed, so an offline farm might still be used in that case.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18263>
 2022-08-26 04:02:15 +00:00
Kenneth Graunke 71ace23fa7 iris: Use linear for exported resources if we can't convey tiling 
If we have modifiers, we can use those to convey the tiling of exported
resources.  If we have the deprecated i915 GET/SET_TILING uAPI, we can
use that to convey the tiling.

If we have neither, then we have to fall back to linear.

Fixes: e658835436 ("iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6938
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18240>
 2022-08-25 16:08:56 -07:00
Jesse Natalie d66e840ab4 dzn: Get max supported shader model 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:49 +00:00
Jesse Natalie 85359eba03 d3d12: Get max supported shader model 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:49 +00:00
Jesse Natalie cb21534a7c microsoft/compiler: Support SM6.7 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:49 +00:00
Jesse Natalie 01b6676d5f microsoft/compiler: SM6.6 is supported 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie 8a4cba7143 microsoft/compiler: Handle SM6.6 handles 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie 15e472f7d2 microsoft/compiler: Pass lower_bound, upper_bound, space to createhandle 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie 6725362dfe microsoft/compiler: Delete double-assignment of sampler metadata field 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie a19628e3c7 microsoft/compiler: Add getters for res bind/props structs 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie b5c6416d40 microsoft/compiler: Add dynamic create handle helper 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie e9489beb76 microsoft/compiler: Add struct and function defs for SM6.6 handle funcs 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie d4b964b546 microsoft/compiler: Support up to shader model 6.5 
We don't actually use any of the new features, but that's okay, it's
still valid DXIL at the higher shader models.

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00
Jesse Natalie ebb9ff2165 microsoft/compiler: Always emit a shader at the max-supported shader model 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18022>
 2022-08-25 21:22:48 +00:00