Commit Graph

74545 Commits

Author SHA1 Message Date
Iago Toral Quiroga f246aa6bca i965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL instructions
The dst is always written, in this case the predicate is only used to select
the value to write, so if we are spilling the dst we always want to write
whatever value we selected to scratch.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-08-07 08:12:50 +02:00
Timothy Arceri 42d283a0cc glsl: remove stage ref generation for transform feedback
Stage ref cannot be queried for transform feedback.

Also simplify the build_stageref function by passing the
correct mode for uniforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-08-07 10:20:08 +10:00
Marek Olšák 6dea2456ca winsys/radeon: add a specific error message for cs_submit -> -ENOMEM
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-07 00:07:10 +02:00
Marek Olšák 42d9f6323a winsys/radeon: add an interface for contexts
Same idea as in libdrm_amdgpu.

A command stream can only be created for a specific context and it's always
submitted to that context.

This will mainly be used by amdgpu and it's required by the GPU reset status
query too.
(radeon only has a basic version of the query and thus doesn't need this)

Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-07 00:06:52 +02:00
Marek Olšák 592ce6e2d1 gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface
The timeout parameter covers both cases.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-07 00:06:13 +02:00
Marek Olšák 8118d3719a radeonsi: rename enable_s3tc -> enable_compressed_formats
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-06 22:54:03 +02:00
Marek Olšák a3723fb9e3 gallium/radeon: add DRM and LLVM version to the renderer string
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 22:54:03 +02:00
Marek Olšák a3e81f819c radeonsi: always flush framebuffer caches at the beginning of IBs
better safe than sorry

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-06 22:54:03 +02:00
Marek Olšák 0615ad1c70 radeonsi: don't count the exact needed CS space if the CS is large enough
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-06 22:54:03 +02:00
Marek Olšák 6d6208a431 radeonsi: don't crash when cleaning up after an incomplete context
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-06 22:54:03 +02:00
Matt Turner 9f78e27fc6 i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.
Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
needed to include no tiling at all, but the name
MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid
confusion by replacing "ALLOC" with "TILING" in the identifiers.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-08-06 12:33:26 -07:00
Matt Turner 1c175fc2e3 i965: Correct a mistake that always forced texture tiling.
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.

The relevant enum values are

   MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5
   MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6
   MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED |
                                    MIPTREE_LAYOUT_ALLOC_XTILED
   MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7

so the expression (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) can
never produce a value of MIPTREE_LAYOUT_ALLOC_LINEAR.

The enum this replaced was

   enum intel_miptree_tiling_mode {
      INTEL_MIPTREE_TILING_ANY,
      INTEL_MIPTREE_TILING_Y,
      INTEL_MIPTREE_TILING_NONE,
   };

where "ANY" means "Y" or "NONE" (i.e., linear). As such, remove the
unused (and worse, unhandled) MIPTREE_LAYOUT_ALLOC_XTILED and redefine
MIPTREE_LAYOUT_ALLOC_ANY_TILED to mean what it did before.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91513
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-08-06 12:33:25 -07:00
Matt Turner 3d551c5c70 i965: Request a miptree with no tiling intel_miptree_map_blit().
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-08-06 12:33:25 -07:00
Marek Olšák 30a7e0c021 radeonsi: add a HUD query showing the number of shaders created
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:37 +02:00
Marek Olšák 70f5e49ba5 radeonsi: add a HUD query showing the number of compiler invocations
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:37 +02:00
Marek Olšák 028528215a gallium/radeon: display cumulative results for some driver queries
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák 18501ff468 gallium/radeon: switch the buffer-wait-time query to microseconds
This display the units in the HUD.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák 0257e1fbd2 gallium/radeon: change some driver query types to Hz
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák dbfeb0ec12 gallium/hud: automatically print % if max_value == 100
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák 4e2a3e0376 gallium/hud: fix printing % next to panes
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák cbad30344d gallium/hud: replace assertions with clamping the unit index
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák 97a65d90fe gallium,hud: allow displaying cumulative values instead of average
The cumulative value is useful for queries like the number of shader
compilations.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák 130a03e360 gallium/hud: fix printing byte units
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák 6b47b89781 gallium,hud: add support for Hz units in driver queries
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák 60159bcfc6 radeonsi: before storing tess levels, load them from LDS instead of temporary
Also use only one store if stride <= 4.
All the fetches from and stores to temporaries can be removed now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91461

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:36 +02:00
Marek Olšák c2a5d1dcb1 winsys/radeon: loosen up the requirements for how much memory IBs can use
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:35 +02:00
Marek Olšák cc59c78b0a gallium/radeon: always use the llvm. prefix in intrinsic names
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2015-08-06 20:44:35 +02:00
Marek Olšák 567394112d radeon/winsys: increase the IB size for VM
Luckily, there is a kernel query, so use the size from that.
It currently returns 256KB. It can be increased in the kernel.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:35 +02:00
Marek Olšák d587742650 gallium/radeon: allow the winsys to choose the IB size
Picked from the amdgpu branch.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:35 +02:00
Marek Olšák 57245cce52 gallium/radeon: suspend timer queries between IBs
When we are measuring the time spent in a draw call, an unexpected flush
can distort the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-06 20:44:35 +02:00
Marek Olšák b2eb13d602 st/mesa: implement DrawTransformFeedbackStream
Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-08-06 20:11:43 +02:00
Marek Olšák 7d3939f0de mesa: save which transform feedback buffer is associated with which stream
Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-08-06 20:11:43 +02:00
Marek Olšák c63e8b1193 vbo: pass the stream from DrawTransformFeedbackStream to drivers
Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-08-06 20:11:43 +02:00
Brian Paul 115964052b mesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()
If the new texture unit is the current texture unit, we can return
before error checking.

Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-06 07:38:47 -06:00
Francisco Jerez ee977183dc i965/fs: Lower arithmetic instructions with register regions of unsupported width.
This extends the SIMD lowering pass to enforce the hardware limitation
that no directly-addressed source may read more than 2 physical GRFs.
One can easily go over this limit when doing 64-bit arithmetic
(e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice
to be able to just emit an instruction of the intended execution size
from the visitor and let the lowering pass deal with this restriction
transparently.

Some hardware arithmetic instructions are not handled here, including
all instructions that use the accumulator implicitly (which the SIMD
lowering pass deliberately doesn't handle), instructions with
non-per-channel sources (e.g. LINE or PLANE) and SEND-like
instructions, which need special handling most likely as virtual
opcodes.

Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2015-08-06 14:12:12 +03:00
Francisco Jerez 42a18ca760 i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.
Otherwise it would crash on Gen8 with scalar VS.  The issue can easily
be reproduced with the following patch, but I don't see any reason why
it wouldn't be possible to end up with an ATTR argument here even
without it.

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2015-08-06 14:12:12 +03:00
Francisco Jerez e77a4a9b1f i965/fs: Implement nir_op_imul/umul_high in terms of MULH.
And get rid of another no16() call.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-06 14:12:12 +03:00
Francisco Jerez 3b48a0eeda i965/fs: Lower the MULH virtual instruction.
Translate MULH into the MUL/MACH sequence.  This does roughly the same
thing that nir_emit_alu() used to do but we can now handle 16-wide by
taking advantage of the SIMD lowering pass.  The force_sechalf
workaround near the bottom is required because the SIMD lowering pass
will emit instructions with non-zero quarter control and we need to
make sure we avoid that on integer arithmetic instructions with
implicit accumulator access due to a known hardware bug on IVB.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-06 14:12:12 +03:00
Francisco Jerez 2e73126438 i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.
In order to make room for the code that will lower the MULH virtual
instruction.  Also move the hardware generation and execution type
checks into the same branch, they are going to have to be different
for MULH.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-06 14:12:12 +03:00
Francisco Jerez f5b37fb1ac i965/fs: Lower 32x32 bit multiplication on BXT.
AFAIK BXT has the same annoying alignment limitation as CHV on the
source register regions of 32x32 bit MULs, give it the same treatment.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-06 14:12:12 +03:00
Francisco Jerez 8f5d0988ea i965: Define virtual instruction to calculate the high 32 bits of a multiply.
This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply.  Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-06 14:12:12 +03:00
Michel Dänzer f7ac4ef4ee glsl: Initialize patch member of glsl_struct_field
There is apparently a subtle difference in C++ between

    F f;

and

    F f();

The former will use the default constructor.  If there is no default
constructor specified, the compiler provides one that simply invokes the
default constructor for each field.  For built-in basic types, the
default constructor does nothing.  The later will, according to
http://stackoverflow.com/questions/2417065/does-the-default-constructor-initialize-built-in-types)
perform value-initialization of the type.  For built-in types this means
initializing to zero.

The per_vertex_accumulator constructor is:

    per_vertex_accumulator::per_vertex_accumulator()
       : fields(),
         num_fields(0)
    {
    }

This is the second form of constructor, so the glsl_struct_field
objects were previously zero initialized.  With the addition of an empty
default constructor in commit 7ac946e5, per_vertex_accumulator::fields
receive no initialization.

Fixes a bunch of random (mostly tessellation related) piglit failures
since commit 7ac946e5 ("glsl: Add constuctors for the common cases of
glsl_struct_field").

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91544
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-08-06 11:53:43 +09:00
Timothy Arceri 2c61d583f8 nir: add missing type to type_size_vec4()
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-08-05 21:16:45 +10:00
Eduardo Lima Mitev 03b7221dbb mesa: Add missing check of format and type in glTexSubImageXD on GLES 3.0
Argument validation for glTexSubImageXD is missing a check of format and type
against texture object's internal format when profile is OpenGL-ES 3.0+.

This patch also groups together all format and type checks on GLES into a
new function texture_format_error_check_gles(), to factorize similar
code in texture_format_error_check().

Fixes 2 dEQP tests:
* dEQP-GLES3.functional.negative_api.texture.texsubimage2d
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-08-05 08:20:16 +02:00
Eduardo Lima Mitev 4b07e9a033 mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal format
Page 161 of the OpenGL-ES 3.1 (PDF) spec, and page 207 of the OpenGL 4.5 (PDF),
both on section '8.6. ALTERNATE TEXTURE IMAGE SPECIFICATION COMMANDS', states:

    "An INVALID_ENUM error is generated if an invalid value is specified for
     internalformat".

It is currently returning INVALID_OPERATION error because
_mesa_get_read_renderbuffer_for_format() is called before the internalformat
argument has been validated. To fix this, we move this call down the validation
process, after _mesa_base_tex_format() has been called. _mesa_base_tex_format()
effectively serves as a validator for the internal format.

Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.texture.copyteximage2d_invalid_format

Fixes 1 piglit test:
* spec@oes_compressed_etc1_rgb8_texture@basic

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
2015-08-05 08:20:16 +02:00
Eduardo Lima Mitev 5d64cae842 mesa: Validate target before resolving tex obj in glTex(ture)SubImageXD
Currently, glTexSubImageXD attempt to resolve the texture object
(by calling _mesa_get_current_tex_object()) before validating the given
target. However, that method explicitly states that target must have been
validated before calling it, so it never returns a user error.

The target validation occurs later when texsubimage_error_check() is called.

This patch reorganizes target validation, taking it out from the error check
function and into a point before the texture object is resolved.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
2015-08-05 08:20:16 +02:00
Eduardo Lima Mitev b38a50f1e3 mesa: Fix errors values returned by glShaderBinary()
Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1,
and page 88 of the OpenGL 4.5 specs state:

    "An INVALID_VALUE error is generated if count or length is negative.
     An INVALID_ENUM error is generated if binaryformat is not a supported
     format returned in SHADER_BINARY_FORMATS."

Currently, an INVALID_OPERATION error is returned for all cases.

Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.shader.shader_binary

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
2015-08-05 08:20:16 +02:00
Tapani Pälli 784bea5a38 mesa: do not modify args when errors with GetProgramResourceName
Original purpose of these lines was to be more friendly against
GUI tools using the extension. However conformance suite explicitly
checks that buffers are not modified in error conditions.

Fixes:
   ES31-CTS.program_interface_query.buff-length

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-08-05 07:26:10 +03:00
Tapani Pälli 18c5cdb943 glsl: add variable mode check to build_stageref
Currently stage reference mask is built using the variable name
only. However it can happen that input of one stage has same name
as output from another stage. Adding check of variable mode makes
sure we do not pick wrong variable.

Fixes some subcases from
   ES31-CTS.program_interface_query.no-locations

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-08-05 07:25:53 +03:00
Frank Binns 7d88413ade dri: set the __DRI_API_OPENGL bit based on max gl compat version
This matches similar behaviour for the __DRI_API_OPENGL_CORE bit.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-04 20:03:16 -07:00