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Author SHA1 Message Date
Sergi Blanch-Torne
acebfc7a38 ci: disable Collabora's farm due to maintenance 
Planned downtime in the farm:
* Start: 2025-06-09 07:00 UTC
* End: 2025-06-09 13:00 UTC

Signed-off-by: Sergi Blanch-Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35304>
 2025-06-09 07:18:34 +02:00
Dave Airlie
870b8717b2 Revert "hasvk/elk: stop turning load_push_constants into load_uniform" 
This reverts commit b036d2ded2.

This seems to break gtk4 and other stuff.

Cc: mesa-stable
(taking ack from Lionel saying we should revert)

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35407>
 2025-06-09 09:20:19 +10:00
Christian Gmeiner
ac042d1178 lima: Convert to use nir_shader_intrinsics_pass 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35130>
 2025-06-08 22:17:39 +00:00
Rob Clark
52d028e06c freedreno: Enable the X1-45 
Enable the GPU in the X1P41200 chipset.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35404>
 2025-06-08 20:18:42 +00:00
Rob Clark
1eef2a65c7 freedreno: Fold X1-85 back into existing dev table entry 
Commit 453ecaddb5 ("freedreno: Remove compute_constlen_quirk") removed
the only UMD visible difference from a740 but did not re-merge the
device table entries.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35404>
 2025-06-08 20:18:42 +00:00
Marek Olšák
bd7efb8805 egl: export GL-CL interop functions from libEGL_mesa.so 
Non-GLVND EGL already exports them.

The PUBLIC un-definition was unnecessary since we use symbols lists.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35386>
 2025-06-08 13:20:47 -04:00
Vinson Lee
8c8496e2f6 freedreno: Sort MRTs so output is stable 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7095
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35402>
 2025-06-08 14:07:50 +00:00
Pavel Ondračka
2859fd34f3 r300: minor fix for backend writer/reader detection 
Consider the following snippet from a Trine shader

 20: RCP temp[40].z, temp[39].__w_;
 21: MOV temp[40].xy, temp[34].-x-y__;
 22: DP3 temp[41].x, temp[40].xyz_, temp[29].xyz_;
...
 33: DP3 temp[52].x, temp[40].xyz_, temp[51].xyz_;
 34: MAX temp[53].x, temp[52].x___, none.0___;
 35: MUL temp[54].xy, temp[40].xy__, const[8].ww__;
 36: MUL temp[55].xy, temp[54].xy__, temp[41].xx__;
 37: MUL temp[56].x, temp[40].z___, const[8].w___;

When we search for writers for temp[40] so that we can check if we can
convert the MUL to omod, the corresponding variable actually contains
the RCP temp[40].z first and the MOV temp[40].xy is marked as friend.
However the current logic only checks the first instruction of variable,
so we fail to find the writer. Just search recursivelly also the
variable friends.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34462>
 2025-06-08 06:29:49 +00:00
Marek Olšák
d279d019d4 ac/nir/tess: remove parameter from and simplify hs_per_patch_output_vmem_offset 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
5734a916d6 ac: move tcs_offchip_layout into ac_shader_args 
It's the same variable between radv and radeonsi, but the implementation of
the load intrinsics is very different.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
5994e08f8b ac: set LDS limit for TCS to 32K for all chips 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
fa5e07d5f7 ac/nir/tess: write TCS patch outputs to memory as vec4 stores at the end 
This moves per-patch output VMEM stores to the end of the shader where they
execute only once. They are skipped if the whole workgroup discards
all patches.

If tcs_vertices_out == 1, per-patch output VMEM stores use the same lanes
as per-vertex output VMEM stores, which are aligned to 4 or 8 lanes to get
cached bandwidth for the stores.

Previously, per-patch outputs were stored to memory for every store_output
intrinsic in TCS.

Additionally, LDS is no longer allocated for per-patch outputs that are only
written and read by invocation 0, or they are written by all invocations
but not read, and don't have indirect indexing. This reduces LDS usage and
LDS traffic.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
c732306c5a ac/nir/tess: unify computing LDS output patch size, minimize LDS bank conflicts 
This unifies the duplicated LDS output patch size computation between
hs_output_lds_offset and ac_nir_compute_tess_wg_info.

"+ 4" to the output patch stride minimizes LDS bank conflicts by making
the beginning of each patch start on a different LDS bank.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
37dc376395 ac/nir/tess: use if-ladder to determine valid tess level components for the vote 
Checking whether every compoment is valid in tess_level_has_effect() when
prim_mode is unknown generated too many SALU. Do this instead:

    if (triangles) ...
        subgroup vote for triangles
    else if (quads) ..
        subgroup vote for quads
    else // isoline
        subgroup vote for isolines

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
2f0d9495c5 ac/nir/tess: inline mask helpers 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
10ae5b2fbf ac/nir/tess: rewrite tess level tracking, don't use LDS for more cases 
This rewrites tess level value tracking to use the 2-bit masks, which
means LDS allocation is determined separately for outer and inner levels.

LDS is not allocated for tess levels that are only written by invocation 0
and never read or only read by invocation 0. If the number of output
patch vertices is 1, LDS is also not allocated for tess levels.

Tess level outputs for TES are always written as whole vec4 to get cached
bandwidth.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
be44da1888 radeonsi: replace tess_levels_written_for_tes mask with a count 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
9d9cfd89da ac/nir/tess: compute the number of remapped VRAM outputs in common code 
This unifies it for both drivers.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
ea70060826 ac/nir/tess: stop using tes_inputs_read / tes_patch_inputs read for TCS & TES 
use ac_nir_tess_io_info instead

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
c38bc4824f ac/nir/tess: apply no_varying to ac_nir_tess_io_info 
This has the effect that no_varying is finally honored for per-patch
outputs, skipping VMEM stores that TES doesn't read.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
f2c48652da nir: add shader_info::tess::tcs_*outputs_read_by_tes* 
Gather no_varying for AMD.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
42445e271e radv,radeonsi: use ac_nir_tess_io_info for LDS size computation 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
c678844ccb ac/nir/tess: move LDS and VMEM output masks into a new info structure 
This will replace LDS and VMEM output size computations in drivers.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
f9c2a01f6a ac/nir/tess: indent a block for nir_if 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
d967266edd ac/nir/tess: if all tess levels are 0, skip per-vertex TCS output stores 
This is done for all chips.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
c1237256cb ac/nir/tess: execute the tess level workgroup vote on all chips 
It will be used to skip stores for discarded patches.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
9c16228359 ac/nir/tess: write TCS per-vertex outputs to memory as vec4 stores at the end 
This improves write throughput for TCS outputs. It follows the same idea
as attribute stores in hw GS. The improvement is easily measurable with
a microbenchmark.

It also has the advantage that multiple output stores to the same address
don't result in multiple memory stores. Each output components gets only
one memory store at the end of the shader.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
509f0e62ad ac/nir/tess: allow passing explicit patch_offset to VMEM/LDS offset calculations 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
a59464b6e3 radv,radeonsi: precompute and pass TCS per-vertex output stride via a user SGPR 
It's a stride of 1 output, which isn't 16. It's 16 * num_threads,
aligned to 256.

tcs_offchip_layout has 5 unused bits, so let's use them.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
742227c65c radv,radeonsi: make TCS_OFFCHIP_LAYOUT_NUM_PATCHES not off by one 
We never use 128 anyway.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
8d3e3c72e0 radv,radeonsi: merge PATCH_CONTROL_POINT & OUT_PATCH_CP into 1 field 
One is only used by TCS, the other is only used by TES.
Use the same field for both, call it PATCH_VERTICES_IN.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák
534b282573 ac/nir/tess: adjust memory layout of TCS outputs to have aligned store offsets 
There is a comment that explains it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:38 +00:00
Marek Olšák
80236f2367 ac/nir/tess: add if/endif for HS threads in NIR instead of ACO/LLVM 
This just removes the if/endif wrapping for LLVM, and hopefully the ACO
change does the same thing.

ACO had redundant code in endif_merged_wave_info, which is removed here.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:38 +00:00
Marek Olšák
cd366b57d9 ac/nir: implement load_subgroup_id/local_invocation_index for TCS on gfx6-10.x 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:38 +00:00
Eric Engestrom
b937d8be9d docs: add sha sum for 25.1.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35401>
 2025-06-07 14:19:55 +00:00
Eric Engestrom
5c25b09002 docs: add release notes for 25.1.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35401>
 2025-06-07 14:19:55 +00:00
Eric Engestrom
1f787ff64e docs: update calendar for 25.1.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35401>
 2025-06-07 14:19:55 +00:00
llyyr
c8bd9ac789 brw: don't unconditionally print message on instance creation 
This would cause Mesa to print this message even if an Intel GPU is just
being enumerated by a Vulkan application. For example, `vulkaninfo
--summary`.

Fixes: 52f73db5b7 ("brw: implement read without format lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35396>
 2025-06-07 13:59:22 +00:00
Pavel Ondračka
16dbcd9b04 r300/ci: add two flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35400>
 2025-06-07 12:12:41 +02:00
Valentine Burley
c6aad1b4c2 khronos-update: Add missing Vulkan Video headers 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35384>
 2025-06-07 05:52:21 +00:00
Guilherme Gallo
f61fe79fc0 ci/turnip: Update a couple of flaky tests on a660-vk 
Got a consecutive timeout in two different `a660-vk` jobs on
`dEQP-VK.subgroups.clustered.compute.subgroupclusteredmax_u64vec4_requiredsubgroupsize`
test.

Analyzed the CI quality stats dashboard [1] (via job name filter) and also
found a flaky
`dEQP-VK.clipping.user_defined.clip_cull_distance.vert_tess_geom.1_7` on
the same job

[1] https://ci-stats-grafana.freedesktop.org/goto/1ai94GLHR?orgId=1

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35377>
 2025-06-07 04:28:49 +00:00
Rob Clark
242f677d20 freedreno: A couple features.txt updates 
Just catching up with reality.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark
0b20bddb8a freedreno: correct resource usage check 
Usage is not a bitmask.  This was causing us to not pick cached-coherent
for staging read buffers (ie. clEnqueueReadBuffer() and friends).

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark
95fede0126 freedreno: Use non-draw batches for compute contexts 
We don't want opencl profiling related queries to create "draw" batches,
as we'd end up with three batches per grid.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark
014b2308c0 freedreno: Fix compute caps 
Get subgroup_sizes and max_compute_units from dev info.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark
57eb3529ac freedreno: Don't autotune if we are already sysmem 
If we've already picked sysmem (for example, non-draw batches) no need
to autotune.  Avoids autotune for compute-only workloads, for example.
Cuts down on per-batch overhead when we get a lot of single grid batches.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark
c5e2e26f49 freedreno: Avoid repeated device lookup 
fd_device_gen() calls fd_dev_info_raw() which loops over all the device
table entries.  No need to do this for every batch.  And we _especially_
don't want to do this per-batch when rusticl cl profiling mode triggers
a batch flush for every launched kernel.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Caleb Callaway
111005066d anv: Increase max VBs to 33 on Gen11+ 
Prior to Gen 11, we had to upload a bunch of SGVs
(FirstVertex, BaseVertex, BaseInstance, DrawID) via
3DSTATE_VERTEX_BUFFERS.

For Gen11+, we upload via 3DSTATE_SGVS_2 instead.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35376>
 2025-06-06 19:32:35 +00:00
Mel Henning
5f0e4a7605 nak,nir: Stop using std::mem::zeroed() 
We can replace all of these with safe alternatives if we ask bindgen for
implementations of Default.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35390>
 2025-06-06 18:58:35 +00:00
Mel Henning
d15b5fadbb nir/divergence_analysis: Update LCSSA comment 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35271>
 2025-06-06 18:15:05 +00:00