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10969 Commits

Author SHA1 Message Date
Tapani Pälli
29fc135a55 anv: use workaround framework for Wa_22018402687 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26925>
 2024-01-10 08:26:41 +00:00
José Roberto de Souza
ad158b0bee anv: Call anv_measure_submit() before anv_cmd_buffer_chain_command_buffers() 
Otherwise the measurement instructions will be placed after the
MI_BATCH_BUFFER_START calling the next cmd_buffer.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
 2024-01-09 14:28:19 +00:00
José Roberto de Souza
d37414d8a4 anv: Fix anv_measure_start/stop_snapshot() over copy or video engine 
Those engines don't have PIPE_CONTROL so we can't do
ANV_TIMESTAMP_CAPTURE_AT_CS_STALL but we can support measurement
by changing the capture type to ANV_TIMESTAMP_CAPTURE_TOP/END_OF_PIPE

Right now this issue is only reproduced in Xe KMD without setting
any special parameters(other than INTEL_MEASURE) because Xe KMD allows
the usage of copy engine while i915 can't due TRTT restrictions.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
 2024-01-09 14:28:19 +00:00
José Roberto de Souza
b8d48ebc93 anv: Add missing anv_measure_submit() calls in Xe KMD backend 
Without this intel_measure don't work with Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
 2024-01-09 14:28:19 +00:00
José Roberto de Souza
a0f7820fe8 anv: Simply companion_rcs handling 
Here dropping is_companion_rcs_cmd_buffer parameter of a few functions
that don't need this information, it just need the right
anv_cmd_buffer for each case.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
 2024-01-09 14:28:18 +00:00
José Roberto de Souza
428a179865 anv: Drop useless STATIC_ASSERT in anv_physical_device_init_queue_families() 
assert(family_count <= ANV_MAX_QUEUE_FAMILIES) already takes care
of STATIC_ASSERT without need of updates.

Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
 2024-01-09 14:28:18 +00:00
José Roberto de Souza
0997766069 anv: Increase ANV_MAX_QUEUE_FAMILIES 
If ANV_VIDEO_DECODE, ANV_VIDEO_DECODE and INTEL_COPY_CLASS are enabled
it is possible to have 5 different queues, so here increasing
ANV_MAX_QUEUE_FAMILIES.

Fixes: 17b8b2cffd ("anv: Add support for a transfer queue on Alchemist")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
 2024-01-09 14:28:18 +00:00
Sviatoslav Peleshko
8e6d28f473 intel/tools/tests: Add i965_asm tests for gfx12 and gfx12.5 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
b87fc2125e intel/tools/tests: Unbreak i965_asm tests 
Currently it's searching for test cases in the nonexistent folders, and
because there are none, tests always pass. Point the script onto the
correct ones. And while we're at it, add a check to make sure this
situation won't repeat in the future.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
bb2083a57c intel/tools/tests: Fix sends indirect argument in gfx9 test 
Currently it's in the wrong format. It was fixed in disasm in
98aab272 ("intel/disasm: Properly disassemble indirect SENDs").
This was accidentally working previously, but isn't accepted after the
changes made to implement send on gfx12.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
98d2461424 intel/tools/i965_asm: Don't set src0 for break and while on gfx12 
This effectively implements same changes as were done to codegen in
bafc9515 ("intel/eu/gen12: Codegen control flow instructions correctly.")

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
db4d58fe31 intel/tools/i965_asm: Add dp4a and add3 instructions 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
88fcd305be intel/tools/i965_asm: Implement gfx12 and gfx12.5 send/sendc 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
bc46cc7807 intel/tools/i965_asm: Allow src0 and src2 of ternary instructions to be imm 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
8eaa0db13f intel/tools/i965_asm: Don't override flag reg from cond modifier 
Both predication and conditional modifier use the same flag, but in
assembly it's specified only once. If the instruction already has a
flag from predication we should not override it with zeroes.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
f96e08f34d intel/tools/i965_asm: Allow neg and abs modifiers on accumulator register 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
98665e024f intel/tools/i965_asm: Handle sync instruction 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
9dd3a6f86f intel/tools/i965_asm: Handle HF immediates 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
0c41a8f5d6 intel/tools/i965_asm: Add SWSB handling 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
cfb34dc695 intel/eu/validate: Validate that the ExecSize is a factor of chosen ChanOff 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
dbf6f0291a intel/fs: Set group 0 for Wa_14010017096 MOV instruction 
We always set exec size to 16 for this MOV, but the execution group remains
from the previous emitted instruction. This can cause emitting a group
which violates PRM restriction for ChanOff: "The execution size (ExecSize)
must be a factor of the chosen offset."

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
173a991405 intel/disasm: Print src1_len correctly depending on ExDesc type 
There are two "Src1.Length" with different formats in "send" description
in the PRMs. One is part of ExMsgDesc, is relevant for LSC SFIDs, and
exists if [ExDesc.IsReg]==false. The other is just a 5-bit immediate,
is relevant for other SFIDs too, and exists if ([ExDesc.IsReg]==true)
AND ([ExBSO]==true).

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
b5c0b90402 intel/compiler: Set flag reg to 0 when disabling predication 
Having the reg set with predication disabled shouldn't cause any problems
during the execution. But when decompiling such instruction the flag won't
be shown in the output, so the recompiling will cause
functionally-identical but binary-different code. Fixing this makes
disasm/asm testing easier.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
a129e136de intel/disasm: Print half-float values instead of placeholder 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
4f41c44df2 intel/compiler: Add variable to dump binaries of all compiled shaders 
This can be useful for testing i965_disasm and i965_asm by comparing
bin -> asm -> bin results.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:51 +00:00
Caio Oliveira
ef88a20d96 intel/compiler: Use INTEL_DEBUG=cs to ask for brw_compiler output 
This removes output like

```
CS SIMD16 shader: 2790 inst, 0 loops, 24804 cycles, 166:106 spills:fills, 35 sends,
  scheduled with mode top-down, Promoted 1 constants, compacted 44640 to 41424 bytes.
```

from the default builds.  Like other debug output in intel_clc, they can
re-enabled with INTEL_DEBUG=cs.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939>
 2024-01-09 01:26:41 +00:00
Caio Oliveira
c21213b438 anv: Don't print warnings for GRL kernel compilations 
Make the build less chatty.  The current warnings are about certain
capabilities not being fully supported, which we don't care for these
particular kernels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939>
 2024-01-09 01:26:41 +00:00
Lionel Landwerlin
4b30b46ffd intel/fs: fix depth compute state for unchanged depth layout 
There is no VK CTS exercising this case. If there was we would run
into hangs as noticed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26876

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26923>
 2024-01-08 17:28:12 +00:00
Lionel Landwerlin
f12ffc6b04 isl: implement Wa_22015614752 
This workaround requires 64Kb alignment for compression with multiple
engine accesses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8614
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26890>
 2024-01-08 08:21:14 +00:00
Lionel Landwerlin
32450d0901 isl: further restrict alignment constraints 
We can limit the AUX-TT requirements to formats supporting CCS.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26890>
 2024-01-08 08:21:14 +00:00
Mark Janes
2236dc3481 intel/dev: update workaround definitions to latest defect status 
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:46 +00:00
Mark Janes
590fe58ef6 intel: remove MTL a0 workarounds 
Meteorlake shipped with the b0 stepping.  Remove fixes for hardware
bugs that were corrected prior to the platform release.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:46 +00:00
Mark Janes
a6a95591aa intel/dev: poison macros for workarounds fixed at a stepping 
INTEL_NEEDS_WA macros are valid when a workaround applies to all
platforms which have the GFX_VERx10 versions for the workaround.

Some workarounds were fixed at a stepping after the platform release.
If a workaround applies partially to any platform, then GFX_VERx10
cannot be used to correctly apply the workaround.

This change invalidates INTEL_NEEDS_WA_16014538804 and
INTEL_NEEDS_WA_22014412737, which were fixed for MTL platforms at
stepping b0.  The run-time checks were already present for all uses of
these macros.  Updating the poisoned macros to INTEL_WA_{num}_GFX_VER
compiles out the run-time checks on platforms where they cannot apply.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:45 +00:00
Mark Janes
7354d3a947 intel/dev: improve descriptions of workaround macros. 
Instructions for INTEL_WA_{num}_GFX_VER macros were confusing and
contradicted itself.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:45 +00:00
Yonggang Luo
d6c258d9ee util: Add align_uintptr and use it treewide to replace ALIGN that works on size_t and uintptr_t 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26866>
 2024-01-05 21:54:35 +00:00
Caio Oliveira
77f4f3112d intel/fs: Use linear allocator in fs_live_variables 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670>
 2024-01-04 23:06:07 +00:00
Caio Oliveira
b5cd91501d intel/fs: Use linear allocator in opt_copy_propagation 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670>
 2024-01-04 23:06:07 +00:00
Caio Oliveira
6d2503e935 intel/fs: Only allocate acp_entry if we are adding one 
In practice it seems we are always entering here, haven't looked
in detail whether at this point we could just assert.  But for now
only allocate a new acp_entry if we are going to add it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670>
 2024-01-04 23:06:07 +00:00
Sagar Ghuge
96e0d979a7 intel/fs: Check fs_visitor instance before using it 
On Xe2+, we don't build the SIMD8 shader so this check makes sure we
don't execute the uninitialized invocations.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26886>
 2024-01-04 22:24:07 +00:00
Dave Airlie
56a72e014f intel/compiler: reemit boolean resolve for inverted if on gen5 
Gen5 adds some boolean conversion instructions after nir emits,
but that nir srcs don't line up with them, so reemit the boolean
conversion if we reemit the inot.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 31b5f5a51f ("nir/opt_if: Simplify if's with general conditions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26782>
 2024-01-04 21:27:23 +00:00
Dave Airlie
8f73cc802c intel/compiler: revert part of "Move earlier scheduler code that is not mode-specific" 
This removed a bunch of calls from the vec4 code that aren't called anywhere else.

Bring back the bits that were removed.

Fixes glxgears on gen5

Fixes: 81594d0db1 ("intel/compiler: Move earlier scheduler code that is not mode-specific")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26862>
 2024-01-04 00:38:38 +00:00
Dave Airlie
37366fef68 intel/compiler: fix release build unused variable. 
This is only used in an assert.

Fixes: 158ac265df ("intel/fs: Make helpers for saving/restoring instruction order")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26863>
 2024-01-03 23:52:11 +00:00
Daniel Schürmann
a3ed36da1a treewide: replace calls to nir_opt_trivial_continues() with nir_opt_loop() 
Totals from 850 (1.11% of 76636) affected shaders: (RADV, GFX11)
MaxWaves: 18134 -> 18130 (-0.02%)
Instrs: 3011298 -> 3008585 (-0.09%); split: -0.17%, +0.08%
CodeSize: 15836804 -> 15841972 (+0.03%); split: -0.09%, +0.12%
VGPRs: 63580 -> 63604 (+0.04%)
SpillSGPRs: 966 -> 1148 (+18.84%); split: -0.83%, +19.67%
Latency: 36102291 -> 30186144 (-16.39%); split: -16.41%, +0.02%
InvThroughput: 9058100 -> 7011821 (-22.59%); split: -22.61%, +0.02%
VClause: 65369 -> 65364 (-0.01%); split: -0.03%, +0.02%
SClause: 100309 -> 100305 (-0.00%); split: -0.04%, +0.04%
Copies: 335658 -> 336472 (+0.24%); split: -0.70%, +0.94%
Branches: 110806 -> 108945 (-1.68%); split: -1.94%, +0.26%
PreSGPRs: 73476 -> 73934 (+0.62%); split: -0.25%, +0.87%
PreVGPRs: 58809 -> 58840 (+0.05%); split: -0.01%, +0.06%

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24940>
 2024-01-03 20:48:04 +00:00
Yonggang Luo
472b6f5379 intel,crocus,iris: Use align64 instead of ALIGN for 64 bit value parameter 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Yonggang Luo
5a2aa3ff88 intel: Cleanup duplicate ALIGN macro defines 
Use ALIGN function instead

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Yonggang Luo
8665ce27bc intel: Use ALIGN_POT instead of ALIGN inside macro define 
These macro define is compute from literals, so use ALIGN_POT instead of ALIGN function
so that it's can be computed at compile time

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Yonggang Luo
3a9c569177 intel: Avoid use align as variable, replace it with other names 
align is a function and when we want use it, the align variable will shadow it
So replace it with other names

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Mark Janes
188c349e51 intel: remove workaround for preproduction DG2 steppings 
DG2_G10 was released with stepping C0.
DG2_G11 was released with stepping B1.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26845>
 2024-01-02 16:06:37 -08:00
Iván Briano
56d556f821 anv: enable VK_KHR_maintenance6 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:02 +00:00
Iván Briano
b7c4fe54cb anv: move astc_emu to use descriptors2 calls 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:02 +00:00