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intel/tools/i965_asm: Add dp4a and add3 instructions

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Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
This commit is contained in:
Sviatoslav Peleshko
2023-10-11 13:21:29 +03:00
committed by Marge Bot
parent 88fcd305be
commit db4d58fe31
2 changed files with 10 additions and 0 deletions
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src/intel/tools/i965_gram.y
+8
View File
@@ -279,6 +279,12 @@ i965_asm_ternary_instruction(int opcode,
case BRW_OPCODE_BFI2:
brw_BFI2(p, dest, src0, src1, src2);
break;
case BRW_OPCODE_DP4A:
brw_DP4A(p, dest, src0, src1, src2);
break;
case BRW_OPCODE_ADD3:
brw_ADD3(p, dest, src0, src1, src2);
break;
default:
fprintf(stderr, "Unsupported ternary opcode\n");
}
@@ -957,6 +963,8 @@ ternaryopcodes:
| BFI2
| LRP
| MAD
| DP4A
| ADD3
;
/* Wait instruction */
src/intel/tools/i965_lex.l
+2
View File
@@ -52,6 +52,7 @@ null { BEGIN(REG); return NULL_TOKEN; }
/* Opcodes */
add { yylval.integer = BRW_OPCODE_ADD; return ADD; }
add3 { yylval.integer = BRW_OPCODE_ADD3; return ADD3; }
addc { yylval.integer = BRW_OPCODE_ADDC; return ADDC; }
and { yylval.integer = BRW_OPCODE_AND; return AND; }
asr { yylval.integer = BRW_OPCODE_ASR; return ASR; }
@@ -76,6 +77,7 @@ do { yylval.integer = BRW_OPCODE_DO; return DO; }
dp2 { yylval.integer = BRW_OPCODE_DP2; return DP2; }
dp3 { yylval.integer = BRW_OPCODE_DP3; return DP3; }
dp4 { yylval.integer = BRW_OPCODE_DP4; return DP4; }
dp4a { yylval.integer = BRW_OPCODE_DP4A; return DP4A; }
dph { yylval.integer = BRW_OPCODE_DPH; return DPH; }
else { yylval.integer = BRW_OPCODE_ELSE; return ELSE; }
endif { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; }