Sviatoslav Peleshko
98d2461424
intel/tools/i965_asm: Don't set src0 for break and while on gfx12
...
This effectively implements same changes as were done to codegen in
bafc9515sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
db4d58fe31
intel/tools/i965_asm: Add dp4a and add3 instructions
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
88fcd305be
intel/tools/i965_asm: Implement gfx12 and gfx12.5 send/sendc
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
bc46cc7807
intel/tools/i965_asm: Allow src0 and src2 of ternary instructions to be imm
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
8eaa0db13f
intel/tools/i965_asm: Don't override flag reg from cond modifier
...
Both predication and conditional modifier use the same flag, but in
assembly it's specified only once. If the instruction already has a
flag from predication we should not override it with zeroes.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
f96e08f34d
intel/tools/i965_asm: Allow neg and abs modifiers on accumulator register
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
98665e024f
intel/tools/i965_asm: Handle sync instruction
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
9dd3a6f86f
intel/tools/i965_asm: Handle HF immediates
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
0c41a8f5d6
intel/tools/i965_asm: Add SWSB handling
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
cfb34dc695
intel/eu/validate: Validate that the ExecSize is a factor of chosen ChanOff
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
dbf6f0291a
intel/fs: Set group 0 for Wa_14010017096 MOV instruction
...
We always set exec size to 16 for this MOV, but the execution group remains
from the previous emitted instruction. This can cause emitting a group
which violates PRM restriction for ChanOff: "The execution size (ExecSize)
must be a factor of the chosen offset."
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
173a991405
intel/disasm: Print src1_len correctly depending on ExDesc type
...
There are two "Src1.Length" with different formats in "send" description
in the PRMs. One is part of ExMsgDesc, is relevant for LSC SFIDs, and
exists if [ExDesc.IsReg]==false. The other is just a 5-bit immediate,
is relevant for other SFIDs too, and exists if ([ExDesc.IsReg]==true)
AND ([ExBSO]==true).
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
b5c0b90402
intel/compiler: Set flag reg to 0 when disabling predication
...
Having the reg set with predication disabled shouldn't cause any problems
during the execution. But when decompiling such instruction the flag won't
be shown in the output, so the recompiling will cause
functionally-identical but binary-different code. Fixing this makes
disasm/asm testing easier.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
a129e136de
intel/disasm: Print half-float values instead of placeholder
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
4f41c44df2
intel/compiler: Add variable to dump binaries of all compiled shaders
...
This can be useful for testing i965_disasm and i965_asm by comparing
bin -> asm -> bin results.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:51 +00:00
Alejandro Piñeiro
54e2e44f99
broadcom/compiler: remove one superfluous call to nir_opt_undef
...
v3d_optimize_nir is calling nir_opt_undef twice. As it is inside the
usual "do {..} while (progress);" loop, is not needed to call it
twice.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26928 >
2024-01-09 12:02:36 +01:00
Italo Nicola
a60c52e5f8
panfrost: expose support for EXT_copy_image
...
This was held back by the issue fixed in the previous patch. Let's
enable it again!
There's a bunch of failures due to a bug in Piglit, where undefined
behavior gets invoked. Let's just mark them as expected failures for now
and move on.
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Italo Nicola
17a62ff993
panfrost: legalize afbc before blitting
...
If we legalize AFBC late, we end up in a situation while we might need
to do a blit while inside a previous blit operation, but u_blitter
state isn't saved recursively, and that leads to crashes.
This patch solves this issue by splitting panfrost_blit into two
functions and legalizing AFBC early.
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Italo Nicola
5027b5aa28
gallium: stop calling resource_copy_region for multisampled copy_image
...
The hook explicitly says it's not supposed to be called for nr_samples > 1.
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Italo Nicola
c6a7d0ead2
panfrost: fix untracked dependency when converting resource modifier
...
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Erik Faye-Lund
3e1708ea40
panfrost: document ci failure
...
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Konstantin Seurer
2e4951d3fb
radv: Remove the BVH depth heuristics
...
It only helps Quake II RTX and hurts everything else.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26481 >
2024-01-09 09:00:24 +00:00
Konstantin Seurer
719619c477
radv: Use PLOC for TLAS builds
...
Improves control performance by about 1%.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26481 >
2024-01-09 09:00:24 +00:00
Dave Airlie
71bd479a7f
radv: don't emit cp dma packets on video rings.
...
Only emit this on the gfx/ace rings.
Fixes hangs with CTS on video decode with navi3x.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26945 >
2024-01-09 07:39:52 +00:00
Sergi Blanch Torne
5cee5578f7
Revert "ci: disable Collabora's LAVA lab for maintance"
...
This reverts commit 11b707de0esergi.blanch.torne@collabora.com >
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26900 >
2024-01-09 07:54:30 +01:00
Caio Oliveira
dc2170f32b
ci: Add Werror=misleading-indentation to debian-clang
...
Due to some issues with GCC and this warning in very long files, we
disabled it when compiling NIR. Unfortunately by design Meson doesn't
allow us to set flags per source file.
The warning is still enabled in clang. but it is less commonly
used during development. To avoid missing catching those warnings,
add -Werror=misleading-indentation to the GitLab CI debian-clang build.
See https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25315 for
more context. This patch is a transcription of what Eric Engestrom
suggested, except only targetting C flags (since we only disable them
for C in NIR build).
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Reviewed-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26938 >
2024-01-09 05:56:16 +00:00
Karol Herbst
6024bbed3c
rusticl/llvm: do not include spirv-tools/linker.hpp
...
This was left by mistake as we do not cache the linked output.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10404
Fixes: 299f949775kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26943 >
2024-01-09 05:12:53 +00:00
Sergi Blanch Torne
ab6f7170e0
Revert "ac/nir: Export clip distances according to clip_cull_mask"
...
This reverts commit b38c776690sergi.blanch.torne@collabora.com >
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26941 >
2024-01-09 02:36:19 +00:00
Caio Oliveira
e0eea5ea4e
nir: Disable -Wmisleading-indentation when compiling with GCC
...
When a file is too large, -Wmisleading-indentantion will give the warning
below, that we can't prevent from a #pragma:
```
src/compiler/nir/nir_opt_algebraic.c: In function ‘nir_opt_algebraic’:
src/compiler/nir/nir_opt_algebraic.c:1469069: note: ‘-Wmisleading-indentation’ is disabled from this point onwards, since column-tracking was disabled due to the size of the code/headers
1469069 | nir_foreach_function_impl(impl, shader) {
|
src/compiler/nir/nir_opt_algebraic.c:1469069: note: adding ‘-flarge-source-files’ will allow for more column-tracking support, at the expense of compilation time and memory
```
See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89549 for details.
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Reviewed-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25315 >
2024-01-09 01:40:22 +00:00
Caio Oliveira
ef88a20d96
intel/compiler: Use INTEL_DEBUG=cs to ask for brw_compiler output
...
This removes output like
```
CS SIMD16 shader: 2790 inst, 0 loops, 24804 cycles, 166:106 spills:fills, 35 sends,
scheduled with mode top-down, Promoted 1 constants, compacted 44640 to 41424 bytes.
```
from the default builds. Like other debug output in intel_clc, they can
re-enabled with INTEL_DEBUG=cs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939 >
2024-01-09 01:26:41 +00:00
Caio Oliveira
c21213b438
anv: Don't print warnings for GRL kernel compilations
...
Make the build less chatty. The current warnings are about certain
capabilities not being fully supported, which we don't care for these
particular kernels.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939 >
2024-01-09 01:26:41 +00:00
Marek Olšák
f09384f4c3
gallium/u_threaded: keep it enabled even if the CPU count is 1
...
radeonsi without TC fails tests.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26584 >
2024-01-08 22:56:41 +00:00
Marek Olšák
b448fb8b8f
gallium/u_threaded: remove unused param from tc_bind_buffer/add_to_buffer_list
...
the tc parameter is unused
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26584 >
2024-01-08 22:56:41 +00:00
Marek Olšák
6327302ec2
gallium/u_threaded: use a dummy end call to indicate the end of the batch
...
instead of using the last pointer. This is simpler.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26584 >
2024-01-08 22:56:41 +00:00
Marek Olšák
a3a6f6855e
mesa,u_threaded_context: add a fast path for glDrawElements calling TC directly
...
mesa/main/draw.c calls threaded_context to add a draw call, but the caller
fills it manually.
This way we don't have to fill pipe_draw_info in a local variable and later
copy it to tc_batch. tc_batch is filled from draw.c directly.
It also eliminates a few conditional jumps thanks to assumptions we can make
in DrawElements but not tc_draw_vbo.
This decreases the overhead of the GL frontend thread by 1.1%, which has
CPU usage of 26%, so it decreases the overhead for that thread by 4.2%.
(1.1 / 26)
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26584 >
2024-01-08 22:56:41 +00:00
Marek Olšák
e04055b90e
gallium/u_threaded_context: use function table to jump to different draw impls
...
Instead of a series of if-else statements, use a function table containing
all the draw variants, which is indexed by:
[is_indirect * 8 + index_size_and_has_user_indices * 4 +
is_multi_draw * 2 + non_zero_draw_id]
This decreases the overhead of tc_draw_vbo by 0.7% (from 4% to 3.3%)
for the GL frontend thread in VP2020/Catia1, which has CPU usage of 26%,
so it decreases the overhead for that thread by 2.7%. (0.7 / 26)
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26584 >
2024-01-08 22:56:41 +00:00
Mike Blumenkrantz
03f049f497
zink: always force flushes when originating from api frontend
...
flags=0 is used for e.g., glFenceSync, which apps use to insert sync points
to determine when all prior work has completed. eliding these flushes into no-ops
is fine for all scenarios except when the last op was a present, in which
case the no-op (previous) fence will not sync as expected for the present and
graphical artifacts will result
in the future, this may be changed back to the previous behavior if/when presentation
gains timeline semaphore capabilities by providing the last timeline id
as a fence instead of the last batch
fixes #10386
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26935 >
2024-01-08 22:37:10 +00:00
Marek Olšák
4ee32ced41
glthread: add proper helpers for call fences
...
These wait for a GL call to be processed by the consumer thread.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26916 >
2024-01-08 22:04:10 +00:00
Marek Olšák
56b4d199a0
glthread: don't unroll draws using user VBOs with GLES
...
The unrolling uses glBegin, which is unsupported by GLES and the GL
dispatch fails.
Fixes: 50d791ca73pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26916 >
2024-01-08 22:04:10 +00:00
Sil Vilerino
311d653df9
d3d12: Fix AV1 Encode - log2 rounding for tile_info section
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26853 >
2024-01-08 19:47:52 +00:00
Konstantin Seurer
da647e7e42
radv/rt/rmv: Log pipeline library creation
...
Pipeline libraries own shaders which take up GPU memory.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26668 >
2024-01-08 19:29:13 +00:00
Konstantin Seurer
84cc494e51
radv/rmv: Fix tracing ray tracing pipelines
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26668 >
2024-01-08 19:29:13 +00:00
Konstantin Seurer
8050b89819
vtn: Handle DepthReplacing correctly
...
The meaning of DepthReplacing was clarified in
https://gitlab.khronos.org/spirv/SPIR-V/-/issues/342 .
TLDR: It just means that the shader can write to FragDepth.
We should therefore only overwrite depth_layout if it is equal to NONE,
since NONE means "not written" and all other modes mean "written" plus
some additional information.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10344
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26876 >
2024-01-08 18:52:50 +00:00
Corentin Noël
0541a57517
virgl: Assert build_id_note before dereferencing it
...
Fix defect reported by Coverity Scan.
Dereference null return value
If the function actually returns a null value, a null pointer dereference will occur.
CID: 1492763
Signed-off-by: Corentin Noël <corentin.noel@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26924 >
2024-01-08 17:44:42 +00:00
Lionel Landwerlin
4b30b46ffd
intel/fs: fix depth compute state for unchanged depth layout
...
There is no VK CTS exercising this case. If there was we would run
into hangs as noticed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26876
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26923 >
2024-01-08 17:28:12 +00:00
Leo Liu
9eac06521a
gallium/vl: match YUYV/UYVY swizzle with change of color channels
...
Update the sampler views with the color channels, that fixes the issue
caused by: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20815
It fixes the case:
`gst-launch-1.0 -v -v filesrc location=file.jpg ! jpegparse ! vaapijpegdec ! imagefreeze ! vaapisink`
Fixes: dc2119bf3fleo.liu@amd.com >
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com >
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26911 >
2024-01-08 17:05:57 +00:00
Pavel Ondračka
8b5cdc5fa5
ci: add r300 RV530 dEQP gles2 CI job
...
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org >
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com >
Reviewed-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26823 >
2024-01-08 16:19:20 +00:00
Pavel Ondračka
6fd41f5416
ci: uprev mesa-trigger container
...
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org >
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com >
Reviewed-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26823 >
2024-01-08 16:19:20 +00:00
Pavel Ondračka
000a8cbb65
r300: fix memory leaks in compiler tests
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26823 >
2024-01-08 16:19:20 +00:00
Timur Kristóf
55e5c4e089
radv: Expose transfer queues, hidden behind a perftest flag.
...
This is highly experimental and only recommended
for users who know what they are doing.
To fully support the spec we are going to need
gang submissions which are going to be implemented later.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com >
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26913 >
2024-01-08 16:00:19 +01:00
