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Author SHA1 Message Date
Marek Olšák 69bc1180b7 radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for compute by buffering reg writes 
This is the compute portion of the work. It uses a separate buffer
for compute SH registers in si_context.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák 1753b321f8 radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for gfx by buffering reg writes 
Instead of writing SH registers into the command buffer, push them into
an array in si_context. Before a draw, take all buffered register writes
and create a single SET_SH_REG_PAIRS_PACKED packet for them.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák a6e6646d91 radeonsi: reorder compute code to prepare for packed SET_SH_REG packets 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák f71607c8d3 radeonsi/gfx11: enable register shadowing by default 
required by SET_SH_REG_PAIRS_PACKED*

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák aafef61f6a radeonsi/gfx11: fix GLCTS with register shadowing by keeping the CS preamble 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák c7f4ffa401 radeonsi: remove uses_reg_shadowing parameter from si_init_gfx_preamble_state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák 913c6392f6 radeonsi: remove radeon_winsys::cs_set_preamble 
It only does radeon_emit_array and it's not possible to do anything better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák c4811edfa6 radeonsi: use si_pm4_create_sized for the shadowing preamble 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák fff585bdb8 radeonsi: don't do BREAK_BATCH for context regs with only 1 context per batch 
because it has no effect

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:55 +00:00
Marek Olšák 835190dd9f radeonsi: keep pipeline statistics disabled when they are not used 
so that we don't always disable/enable pipeline stats around blits
when there are no pipeline stat queries

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:54 +00:00
Marek Olšák ccb856fbaa radeonsi: determine si_pm4_state::reg_va_low_idx automatically 
The existing code doesn't work with the packed SET packets, so si_pm4_state
needs to find reg_va_low_idx after the whole packet is built.

Remove si_pm4_set_reg_va and do the same thing for SET_SH_REG.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:54 +00:00
Marek Olšák 22f3bcfb5a radeonsi/gfx11: use SET_*_REG_PAIRS_PACKED packets for pm4 states 
It can generate all PACKED packets, but only SET_CONTEXT_REG_PAIRS_PACKED
is generated because register shadowing is required by
SET_SH_REG_PAIRS_PACKED*.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:54 +00:00
Marek Olšák 1aa99437d3 radeonsi: eliminate redundant TCS user data and RSRC2 register changes 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:54 +00:00
Marek Olšák 6959493f8c radeonsi: move the only tcs_out_lds_offsets field to vs_state_bits 
This removes 1 user data SGPR.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:54 +00:00
Marek Olšák 5632d8d1a7 radeonsi: replace tcs_out_lds_layout with nearly identical tes_offchip_addr 
tcs_out_lds_layout is basically renamed to tes_offchip_addr in TCS, using
the same variable as TES and also using the same bit layout. The only
difference in the bit layout was that TCS had to mask out the low bits,
which this also removes.

The enums are renamed to *_SGPR_TCS_OFFCHIP_ADDR so as not to conflict
with *_SGPR_TES_OFFCHIP_ADDR, which are in different user data SGPRs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:54 +00:00
Marek Olšák 1b40ab2150 radeonsi: move TCS.gl_PatchVerticesIn into the tcs_offchip_layout SGPR 
we'll be able to remove 1 TCS user data SGPR thanks to this

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
 2023-06-22 08:35:54 +00:00
Martin Roukala (né Peres) b4e2073f04 zink/ci: remove 3 tests from the fails list 
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>
 2023-06-22 08:10:06 +00:00
Martin Roukala (né Peres) 4031ed5c8a amd/ci: temporarily disable some manual jobs that take a long time to run 
We are trying to re-enable the valve CI... but doing so runs all the
jobs, including the manual ones.

Since some can take over an hour to run, let's disable them, and
re-enable them in another MR by reverting this commit.

Sorry for the noise!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>
 2023-06-22 08:10:06 +00:00
Martin Roukala (né Peres) a4796a34b1 Revert "ci: mark the valve farm as down" 
Fixed by rebooting the gateway. A post-mortem analysis will be
performed to figure out what happened!

This reverts commit 2089fc8188.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>
 2023-06-22 08:10:06 +00:00
Pavel Ondračka b4ca45911d nir_opt_algebraic: don't use i32csel without native integer support 
Otherwise nir_lower_int_to_float (or specifically nir_gather_ssa_types)
will fail to recognize we already have float constants and converts them
again.

Example from spec/glsl-1.10/execution/vs-loop-array-index-unroll.shader_test
with r300 driver (after enabling has_fused_comp_and_csel).

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x3e800000, 0x3f800000) = (0.000000, 0.250000, 1.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x3f000000, 0x3f800000) = (0.000000, 0.500000, 1.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x3f400000, 0x3f800000) = (0.000000, 0.750000, 1.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x3f800000) = (0.000000, 1.000000)
        vec1 32 ssa_6 = load_const (0x3f800000 = 1.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x00000001, 0x00000002, 0x00000003) = (0.000000, 0.000000, 0.000000, 0.000000)
        vec4  1 ssa_9 = ilt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_15 = i32csel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_15.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

and after nir_lower_int_to_float

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x4e7a0000, 0x4e7e0000) = (0.000000, 1048576000.000000, 1065353216.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x4e7c0000, 0x4e7e0000) = (0.000000, 1056964608.000000, 1065353216.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x4e7d0000, 0x4e7e0000) = (0.000000, 1061158912.000000, 1065353216.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x4e7e0000) = (0.000000, 1065353216.000000)
        vec1 32 ssa_6 = load_const (0x4e7e0000 = 1065353216.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x3f800000, 0x40000000, 0x40400000) = (0.000000, 1.000000, 2.000000, 3.000000)
        vec4  1 ssa_9 = flt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_13 = fcsel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_13.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23704>
 2023-06-22 07:25:44 +00:00
Eric Engestrom f9a4b8e640 docs/ci: fix command to disable/re-enable farms 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23780>
 2023-06-22 07:17:31 +00:00
Gert Wollny e853332805 r600/sfn: Add source mod propagation also to fp64 ops 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>
 2023-06-22 06:31:50 +00:00
Gert Wollny 255eee10ac r600/sfn: Implement fsat for 64 bit ops 
Because a plain mov with the fsat modifier doesn't do a proper 64 bit fsat
we either have to propagate the op as modifier to the instruction that
creates the value, or we add a fake op that applies the fsat op, i.e. we
implement the mov as an add_64 with zero as the second value.

Fixes:  0ff3c4bef2
    r600/sfn: drop use of nir source mods

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>
 2023-06-22 06:31:50 +00:00
Iván Briano 12d86e9822 anv: update conformanceVersion 
The Vulkan CTS started generating the list of valid versions the driver
can report as conformant against based on the active branches, and the
1.3.0 branch we were reporting up to now is no longer valid.

Fixes dEQP-VK.api.driver_properties.conformance_version

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23784>
 2023-06-22 01:28:32 +00:00
Jesse Natalie ff52a00553 dzn: Align placed footprints used when copying linear <-> optimal for BC formats 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23662>
 2023-06-22 00:57:20 +00:00
Helen Koike 9dd106b113 ci: move .microsoft-farm-container-rules to test-source-dep.yml 
farm rules are placed on test-source-dep.yml, so move it there.

This is also useful when trying to re-use the container/gitlab-ci.yml to
other workflows without running the jobs.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23731>
 2023-06-22 00:01:18 +00:00
Mike Blumenkrantz 402ae3b132 nir/lower_tex: ignore saturate for txf ops 
saturate is used for GL_CLAMP emulation, and GL_CLAMP cannot be used
with txf

ref #9226

cc: mesa-stable

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23750>
 2023-06-21 23:13:50 +00:00
Mike Blumenkrantz 886b7aaa6b zink: add fastpaths for no-op sampler/view rebinds 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:48 +00:00
Mike Blumenkrantz 8125437acd zink: check sampler views pointer before loop 
this doesn't need to be checked in every loop iteration

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:48 +00:00
Mike Blumenkrantz 58b82d231d zink: don't update tc info directly from cso binds 
this somehow becomes expensive at extremely high fps, so defer
until rp begin to check layout change state

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:48 +00:00
Mike Blumenkrantz 7b4c1b3a42 zink: track and apply ds3 states only on change 
drivers don't do their own state tracking, so ensure the calls are only
made when necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:48 +00:00
Mike Blumenkrantz 5dc2d329cb zink: use local screen var in blend state bind 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:47 +00:00
Mike Blumenkrantz 2543fc15a1 zink: clean up rp update tracking on dsa bind 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:47 +00:00
Mike Blumenkrantz b65efda508 zink: specialize invalidate_descriptor_state hook for compact mode 
the constant flag check here has perf implications at high fps,
so avoid it when possible

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:47 +00:00
Mike Blumenkrantz 53542dd120 zink: make invalidate_descriptor_state a ctx hook 
this will allow for specialization

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:47 +00:00
Mike Blumenkrantz ad04bd81b9 zink: force inlining for a bunch of functions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:47 +00:00
Mike Blumenkrantz 14bf10c1ad zink: no-op redundant samplemask changes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
 2023-06-21 22:43:47 +00:00
Jesse Natalie f759cbb675 dzn: Fix multisample counts in device limits 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>
 2023-06-21 22:27:08 +00:00
Jesse Natalie 8b888ead2f dzn: Remove dynamic check for block-compressed support 
None of this is optional in D3D

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>
 2023-06-21 22:27:08 +00:00
Jesse Natalie a3d14e4b05 dzn: Use common GetPhysicalDeviceFeatures2 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>
 2023-06-21 22:27:08 +00:00
Jesse Natalie 7a68617692 dzn: Inline D3D12 device creation in physical device creation 
This was effectively happening *anyway* because WSI init was calling
functions that needed a D3D12 device around to be able to answer.
Just remove the whole song and dance of maybe not having a device.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>
 2023-06-21 22:27:08 +00:00
Michel Zou badb85edb8 util: reinstate ENUM_PACKED 
gets rid of warning: 'gcc_struct' attribute ignored [-Wattributes] introduced by !23338

Fixes: 86532fa21d ("util: Use the gcc_struct attribute for packed structures in mingw")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23478>
 2023-06-21 21:51:59 +00:00
Alexander von Gluck IV 4b48d377ba egl/haiku: Fix potential crash if double buffering is disabled 
* Don't assume the existence of the back buffer in swap_buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23556>
 2023-06-21 21:18:28 +00:00
Eric Engestrom 2089fc8188 ci: mark the valve farm as down 
docker daemon is down on mupuf-gfx10-vangogh-{1..3}

Signed-off-by: Eric Engestrom <eric@igalia.com>
 2023-06-21 21:34:25 +01:00
Ian Romanick ed5d346868 intel/fs: Add missing newline 
Emacs will add a newline to the end of this file whether I've edited
that line or not. It was driving me up the wall, so... yeah.

Trivial.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23777>
 2023-06-21 19:57:58 +00:00
Mike Blumenkrantz df6749ed56 radv: inline radv_can_enable_dual_src() 
this is unexpectedly heavy

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>
 2023-06-21 18:59:07 +00:00
Mike Blumenkrantz 8b73109a93 radv: remove redundant intermediate variable in radv_is_mrt0_dual_src() 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>
 2023-06-21 18:59:07 +00:00
Jesse Natalie 2a1d97e3fc dzn: Ignore export access parameters 
D3D requires these to just be GENERIC_ALL. Fixes some sharing tests.

Fixes: c64f1b66 ("dzn: Hook up win32 semaphore import/export")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23772>
 2023-06-21 18:31:28 +00:00
Eric Engestrom 63f44951ac asahi: drop unnecessary DRM_FORMAT_MOD_{LINEAR,INVALID} fallbacks 
Since afe134a49c ("asahi: Drop macOS backend"), `drm_fourcc.h` is
unconditionally included, meaning these defines are now dead code.

Fixes: afe134a49c ("asahi: Drop macOS backend")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23773>
 2023-06-21 18:17:56 +00:00
Rhys Perry cfa7eec06c aco: don't set exec_hi for wave32 scan reductions 
fossil-db (wave32):
Totals from 21 (0.02% of 133428) affected shaders:
Instrs: 10778 -> 10712 (-0.61%)
CodeSize: 56604 -> 56208 (-0.70%)
Latency: 168293 -> 168251 (-0.02%)
InvThroughput: 25256 -> 25253 (-0.01%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23745>
 2023-06-21 17:58:44 +00:00