radeonsi: remove radeon_winsys::cs_set_preamble

It only does radeon_emit_array and it's not possible to do anything better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
This commit is contained in:
Marek Olšák
2023-06-10 21:49:19 -04:00
committed by Marge Bot
parent c4811edfa6
commit 913c6392f6
6 changed files with 3 additions and 28 deletions
+3 -3
View File
@@ -421,9 +421,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
if (ctx->cs_preamble_state) {
struct si_pm4_state *preamble = is_secure ? ctx->cs_preamble_state_tmz :
ctx->cs_preamble_state;
ctx->ws->cs_set_preamble(&ctx->gfx_cs, preamble->pm4, preamble->ndw,
preamble != ctx->last_preamble);
ctx->last_preamble = preamble;
radeon_begin(&ctx->gfx_cs);
radeon_emit_array(preamble->pm4, preamble->ndw);
radeon_end();
}
if (!ctx->has_graphics) {
-1
View File
@@ -1038,7 +1038,6 @@ struct si_context {
struct pipe_scissor_state window_rectangles[4];
/* Precomputed states. */
struct si_pm4_state *last_preamble;
struct si_pm4_state *cs_preamble_state;
struct si_pm4_state *cs_preamble_state_tmz;
uint16_t gs_ring_state_dw_offset;
@@ -3876,7 +3876,6 @@ bool si_update_gs_ring_buffers(struct si_context *sctx)
}
/* Flush the context to re-emit both cs_preamble states. */
sctx->last_preamble = NULL; /* flag that the preamble has changed */
sctx->initial_gfx_cs_size = 0; /* force flush */
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
@@ -4143,7 +4142,6 @@ void si_init_tess_factor_ring(struct si_context *sctx)
/* Flush the context to re-emit the cs_preamble state.
* This is done only once in a lifetime of a context.
*/
sctx->last_preamble = NULL; /* flag that the preamble has changed */
sctx->initial_gfx_cs_size = 0; /* force flush */
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
}
@@ -526,19 +526,6 @@ struct radeon_winsys {
struct pipe_fence_handle **fence),
void *flush_ctx, bool allow_context_lost);
/**
* Set or change the CS preamble, which is a sequence of packets that is executed before
* the command buffer. If the winsys doesn't support preambles, the packets are inserted
* into the command buffer.
*
* \param cs Command stream
* \param preamble_ib Preamble IB for the context.
* \param preamble_num_dw Number of dwords in the preamble IB.
* \param preamble_changed Whether the preamble changed or is the same as the last one.
*/
void (*cs_set_preamble)(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib,
unsigned preamble_num_dw, bool preamble_changed);
/**
* Set up and enable mid command buffer preemption for the command stream.
*
@@ -1114,13 +1114,6 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
return true;
}
static void amdgpu_cs_set_preamble(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib,
unsigned preamble_num_dw, bool preamble_changed)
{
/* TODO: implement this properly */
radeon_emit_array(cs, preamble_ib, preamble_num_dw);
}
static bool
amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_ib,
unsigned preamble_num_dw)
@@ -1965,7 +1958,6 @@ void amdgpu_cs_init_functions(struct amdgpu_screen_winsys *ws)
ws->base.ctx_destroy = amdgpu_ctx_destroy;
ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
ws->base.cs_create = amdgpu_cs_create;
ws->base.cs_set_preamble = amdgpu_cs_set_preamble;
ws->base.cs_setup_preemption = amdgpu_cs_setup_preemption;
ws->base.cs_destroy = amdgpu_cs_destroy;
ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
@@ -845,7 +845,6 @@ void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
ws->base.ctx_destroy = radeon_drm_ctx_destroy;
ws->base.ctx_query_reset_status = radeon_drm_ctx_query_reset_status;
ws->base.cs_create = radeon_drm_cs_create;
ws->base.cs_set_preamble = radeon_drm_cs_set_preamble;
ws->base.cs_destroy = radeon_drm_cs_destroy;
ws->base.cs_add_buffer = radeon_drm_cs_add_buffer;
ws->base.cs_lookup_buffer = radeon_drm_cs_lookup_buffer;