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Author SHA1 Message Date
Marek Olšák
c79697fec5 winsys/amdgpu: skip code checking RADEON_USAGE_SYNCHRONIZED for slabs 
We unset RADEON_USAGE_SYNCHRONIZED, but we still checked it.
Iterate over such buffers separately without checking
RADEON_USAGE_SYNCHRONIZED.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:25 -05:00
Marek Olšák
0911aea126 winsys/amdgpu: merge 2 loops iterating over real BOs in amdgpu_cs_submit_ib 
The first loop updates sequence numbers. The second loop creates the BO list.
Do both in the same loop.

Each loop has to reload the whole BO list from the L2 cache or higher, so we
do it twice. By merging the loops, we only load the BO list from the L2
cache once.

The final result is actually 2 loops, but they iterate over different ranges
of the BO list, so each element is read only once.

If global_bo_list is enabled, it overwrites the BO list after all is done.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:22 -05:00
Marek Olšák
d704f92b13 winsys/amdgpu: merge 2 loops iterating over sparse BOs in amdgpu_cs_submit_ib 
The first loop is inside amdgpu_add_sparse_backing_buffers. The second loop
iterates over sparse BOs to update sequence numbers.

Each loop has to reload the whole BO list from the L2 cache or higher, so we
do it twice. By merging the loops, we only load the BO list from the L2
cache once.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:20 -05:00
Marek Olšák
32625c7903 winsys/amdgpu: merge 2 loops iterating over slab entries in amdgpu_cs_submit_ib 
The first loop is inside amdgpu_add_slab_backing_buffers. The second loop
iterates over BOs to update sequence numbers.

Each loop has to reload the whole BO list from the L2 cache or higher, so we
do it twice. By merging the loops, we only load the BO list from the L2
cache once.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:18 -05:00
Marek Olšák
77e96cec6e winsys/amdgpu: move code out of amdgpu_add_bo_fences_to_dependencies for reuse 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:16 -05:00
Marek Olšák
436ebe4ef6 winsys/amdgpu: change the signature of amdgpu_add_bo_fences_to_dependencies 
for future work

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:14 -05:00
Marek Olšák
75ffd738ac winsys/amdgpu: add real buffers of slab entries in the CS thread 
This removes the overhead from the driver thread and simplifies
amdgpu_cs_add_buffer.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:12 -05:00
Marek Olšák
41f6d24fc8 winsys/amdgpu: fix a race condition when reading ws->num_buffers 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
 2024-02-07 02:30:10 -05:00
Jordan Justen
4957d352dd intel/dev: Add device info for ARL 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
964042d50c anv/query: Follow MTL code paths on ARL 
Ref: 0a52002a1c ("anv: disable reset query pools using blorp opt on MTL")
Ref: b3b12c2c27 ("anv: enable CmdCopyQueryPoolResults to use shader for copies")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
c1ffd0a037 anv/drirc: Extend option to disable FCV optimization to ARL 
Ref: 01046cd6ad ("anv/drirc: add option to disable FCV optimization")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
c3a0483f5b intel/compiler: Lower DPAS instructions on ARL except ARL-H 
Ref: bspec 55414
Ref: 951e08fc18 ("intel/compiler: Disable DPAS instructions on MTL")
Suggested-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
e2b09b8559 isl: Handle ARL in isl_drm_modifier_get_score() 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
9ce0fe460a isl: Define MOCS for ARL 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
362ccd3874 intel/dev: Define engine prefetch for ARL 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
c616ce8153 intel/i915: ARL also supports the set-PAT uapi 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
edf93db5ee iris: Extend MTL modifiers to ARL devices 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
a443a824ad intel/l3: Define l3 config for ARL 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
546652b31a intel/dev: Add intel_device_info_is_mtl_or_arl() 
MTL and ARL share many code paths, and this macro will make it easier
to check for either of them.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
Jordan Justen
1d08282060 intel/dev: Add ARL platform enums 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
 2024-02-06 21:23:19 +00:00
David Rosca
fa8e0ba3f7 frontends/va: Fix updating AV1 rate control parameters 
Follow the same logic as H264.

Fixes: 5edbecb856 ("frontends/va: adding va av1 encoding functions")

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27481>
 2024-02-06 21:07:28 +00:00
Eric Engestrom
cff5bc5af7 pvr: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:39 +00:00
Eric Engestrom
58e7085cb0 lvp: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:39 +00:00
Eric Engestrom
bb0791535a vn: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
7667802b7d panvk: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
64081b9f46 nvk: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
5f373dec88 dzn: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
b10f61f98e hasvk: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
32800aa1d7 anv: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
6407d0f0a2 tu: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
11cf6965ea v3dv: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Eric Engestrom
faad4ffe97 radv: enable VK_EXT_headless_surface on all platforms except Windows 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448>
 2024-02-06 20:32:38 +00:00
Samuel Pitoiset
ffbd3e5b2d radv: change the user SGPR idx of AC_UD_TES_STATE 
When GS will be compiled separately, we will have to always declare
both VS and TES user SGPRs because we can't know the previous stage,
and the shader input arguments must match and mustn't overlap.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
 2024-02-06 20:12:38 +00:00
Samuel Pitoiset
3e9815173a radv: set the default workgroup size for VS/TES as ES 
If shaders are linked, the optimal value would be computed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
 2024-02-06 20:12:38 +00:00
Samuel Pitoiset
90e354afb0 radv: determine the workgroup size for GS non-NGG earlier 
The wavesize for VS/TES/GS is always the same, so this can be computed
earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
 2024-02-06 20:12:38 +00:00
Samuel Pitoiset
35c9631162 radv: determine the ES stage earlier when processing binary config 
This will help implementing VS+GS and TES+GS compiled separately on
GFX9+ because the shader config will need to be combined.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
 2024-02-06 20:12:38 +00:00
Samuel Pitoiset
03314b2a86 radv: check for MESA_SHADER_TESS_EVAL in radv_fill_shader_info_ngg() 
This seems clearer to me.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
34572d535e radv: use next_stage to determine the NGG stage 
This shouldn't change anything, except that it will help for ESO.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
31f006d352 radv: always set GS as NGG if present on GFX11 
GFX11 is full NGG.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
55093270ed radv: squash GFX10/GFX10.3 NGG restrictions in the same condition 
They don't apply on GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
237ab5db86 radv: remove one indentation level in radv_fill_shader_info_ngg() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
David Heidelberg
010272b62e util: use crc32_z instead of crc32 and bump zlib dep to 1.2.9 
1.2.9 has been released in January 2017, so let's assume
we'll find it everywhere.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27311>
 2024-02-06 19:22:53 +00:00
David Heidelberg
56f31d1847 meson: upgrade zlib wrap to 1.3.1 
`$ meson wrap update zlib`

Cc: mesa-stable
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27311>
 2024-02-06 19:22:53 +00:00
Pavel Ondračka
238c3d593b r300/ci: update piglit fails 
Most likely changed by recent piglit uprev.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27493>
 2024-02-06 17:32:13 +00:00
Eric Engestrom
f9acd9e659 v3dv/ci: test the WSI on rpi4 and rpi5 
Add a few tests to the skip list because they take over a minute to finish.

All the other new tests run in less than 50 seconds.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27315>
 2024-02-06 17:15:07 +00:00
Christian Gmeiner
7c198d4404 isaspec: encode.py: Include assert.h 
pack_field(..) makes use of assert(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27491>
 2024-02-06 16:38:01 +00:00
Zan Dobersek
c3b667d488 tu/msm: fix RD_CHIP_ID size used when dumping RD 
The chip ID field size is 8 bytes across fd_dev_id and different RD tools.
The call to fd_rd_output_write_section for RD_CHIP_ID should be fixed to
use the proper size as well.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27430>
 2024-02-06 16:01:20 +00:00
Rhys Perry
4f6aac1589 aco/tests: fix to_hw_instr.swap_linear_vgpr 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27436>
 2024-02-06 15:40:58 +00:00
Rhys Perry
174e37afb9 aco: fix >8 byte linear vgpr copies 
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27436>
 2024-02-06 15:40:58 +00:00
Hsieh, Mike
33d88f797b amd/vpelib: Add UID for 3d Lut and control logic 
[WHY]
3D lut generation takes time, we need to cache it and identify it as it
updated.

[HOW]
Add unique id when new 3d lut is generated.
Add control logic with UID.

Reviewed-by: Jesse Agate <jesse.agate@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00