Commit Graph

10454 Commits

Author SHA1 Message Date
Chia-I Wu b653669fc5 anv: add gen9 astc workaround
gen9 does not handle denorms in void extent blocks correctly.  We need
to flush them to zero.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25800>
2023-10-25 00:06:04 +00:00
Chia-I Wu c42b1a5a74 anv: prep for gen9 astc workaround
We will reuse astc emu for gen9 astc workaround.  This commit contains
minor cleanups and has no functional change.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25800>
2023-10-25 00:06:04 +00:00
Caio Oliveira b91ed68fa0 intel/compiler: Don't emit calls to validate() in release build
While the fs_visitor::validate() implementation is empty in release
build, we still emit calls to it since it is defined in a separate
compilation unit than its callers.  To fix this, just expose an inline
empty function in the header for the release mode.

Fossil run time differences in TGL laptop (difference at 95.0% confidence):

```
Rise of The Tomb Rider (Native) [n=7]
        -0.482857 +/- 0.010932
        -1.60608% +/- 0.0363621%

Cyberpunk 2077 (DXVK) [n=7]
        -0.987143 +/- 0.0904516
        -0.82996% +/- 0.076049%

Batman Arkham City (DXVK) [n=7]
        -7.74857 +/- 0.329561
        -1.46298% +/- 0.0622231%
```

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25847>
2023-10-24 21:10:35 +00:00
Rohan Garg 3bf1b7deba anv: selectively enable FCV optimization for DG2
Enabling FCV on MTL breaks a number of games and benchmarks. Let's
disable it for now till we can root cause the issue.

Closes: #9987
Fixes: 26c2c9 ('anv: enable FCV for Gen12.5')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25863>
2023-10-24 19:27:14 +00:00
Rohan Garg 25a232238f anv: turn off non zero fast clears for CCS_E
This helps fix a performance regression on games such as F1 22 and RDR2.
Turning on non zero fast clears causes additional partial resolves for
these games that degrades performance. Let's turn off non zero fast
clears till we can eliminate the partial resolves.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25863>
2023-10-24 19:27:14 +00:00
Rohan Garg f85d8d908c anv: cleanup includes
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25766>
2023-10-24 10:33:57 +00:00
José Roberto de Souza bd546f9e54 anv: Switch Xe KMD vm bind to sync
It was never actually async as it was doing a DRM_IOCTL_SYNCOBJ_WAIT
right after DRM_IOCTL_XE_VM_BIND but it was required to allow the
partial binds required by sparse.
But it is now fixed and we can switch back to sync vm bind.

In future we will switch back to async vm bind to improve performance
but this time it will be properly implemented.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25300>
2023-10-23 23:24:26 +00:00
José Roberto de Souza 531605accf intel: Sync xe_drm.h
Sync xe_drm.h with commit xxxxx ("drm/xe/uapi: Fix naming of XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY").

One not so straght forward change is that sync VM binds now don't
require a syncobj anymore, the uAPI will return as soon the VM bind
operations are done.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25300>
2023-10-23 23:24:26 +00:00
Nanley Chery d57611fe25 intel/isl: Add scores for GEN12_RC_CCS and MTL_RC_CCS
Now that these CCS-enabled modifiers have non-zero scores, anv is
enabled to use them.

We found this to improve the performance of Borderlands 3 by 18.73%.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6701
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Tested-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery 9e402e93d2 anv: Delete implicit CCS code
Stop allocating CCS at the end of some BOs. Anv no longer uses that
memory range.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery 4cdd3178fb anv: Meet CCS alignment reqs with dedicated allocs
At image bind time, we require BOs to meet aux-map alignment
requirements in order to enable CCS on images. This is a heuristic
controlled by anv_bo_allows_aux_map().

To improve the chances of getting a properly aligned BO, we make use of
the dedicated allocation extension. Firstly, we report to applications a
preference for dedicated memory if an image would like to use the aux
map. Secondly, we align the VMA for dedicated allocations to meet
aux-map requirements.

To make enabling modifiers much easier on integrated gfx12, report
dedicated allocations as a requirement for modifiers which specify CCS.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery 2cbec81041 anv: Loosen anv_bo_allows_aux_map
Instead of requiring that a BO has the has_implicit_ccs flag set, simply
require that the BO is aligned according to aux-map requirements.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery ee6e2bc4a3 anv: Place images into the aux-map when safe to do so
At image bind time, if an image's addresses can be placed into the
aux-map without causing conflicts with a pre-existing mapping, do so.
The code aux management code in the binding function operates on a
per-plane basis. So, use the per-plane CCS memory range from the image
rather than the CCS memory region for the entire BO.

Another way to avoid aux-map conflicts is to rely solely on having a
dedicated allocation for an image. Unfortunately, not all workloads
change their behavior when drivers report a preference for dedicated
allocations. In particular, 3DMark Wild Life Extreme does not make more
dedicated allocations and such a solution was measured to perform ~16%
worse than this solution. With this solution, I did not measure a loss
of CCS on that benchmark.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6304
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery 207db22117 anv: Refactor CCS disabling at image bind time
Split out the discrete and integrated implicit CCS cases. We'll do more
work in the integrated case in a future commit.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery d31c62f384 anv: Wrap aux surface image binding queries
Add and use anv_image_get_aux_memory_range.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery cd12eec496 anv: Allocate space for aux-map CCS in image bindings
This makes images a bit larger by reserving space to store the
compression control surface when the device uses an aux-map.

This space is not used currently because anv still maps main surface
addresses to space at the end of the anv_bo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery 5e07255148 anv: Move scope of CCS binding determination
Move the determination of the image binding for CCS to a larger scope,
so that it can be reused for other aux usages in
add_aux_surface_if_supported().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Nanley Chery b1a14fe923 intel: Return a bool from intel_aux_map_add_mapping
Make intel_aux_map_add_mapping return false if a mapping is attempted
that would conflict with an existing one. If this function doesn't
return false, it will either fail to return or return true.

The Vulkan driver will make use of this feature to opportunistically
enable CCS if a BO's VMA range has not been already mapped.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
2023-10-23 21:37:24 +00:00
Lionel Landwerlin 454870dd5f anv: merge gfx9/11 indirect draw generation shaders
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin 11b4c23d19 anv: add ring buffer mode to generated draw optimization
When the number of draw calls is very large, instead of allocating
large amounts of batch buffer space for the draws, use a ring buffer
and process the draw calls by batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8645
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin 718e77eee5 anv: index indirect data buffer with absolute offset
This will help for a follow up change where we will respawn the shader
multiple times in a loop and the base offset will be edited by the
shader itself.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin db335d9b73 anv: factor out host/gpu internal shaders interfaces
This will prevent host/gpu structure definitions to go out of sync.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin c700d47c56 anv: move generation batch fields to a sub-struct
Just tyding things a bit since we're about to add more.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin 2e0ff4c551 anv: avoid MI commands to copy draw indirect count
We can just make the address of the count available to the generation
shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin 1af1085d76 anv: identify internal shader in NIR
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin d5aec0ca4b anv: extract out draw call generation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin 8ab3c03a32 anv: fix generated draws gl_DrawID with more than 8192 indirect draws
This applies only to Gfx9.

We're writting out of bounds to a wrong location.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1d9cf8f381 ("anv: add gfx9 generated draw support")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin 8aadd4745c anv: move generation shader return instruction to last draw lane
If we dispatch exactly a multiple of 8192 items, there is additional
lane left to generate the jump instruction.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>
2023-10-20 13:07:53 +00:00
Lionel Landwerlin 5d76b03a3e anv: uninitialize queues before utrace
We need to shut down the runtime queue threads before tearing down
anything else.

Gets rid of helgrind errors like this :

==212772== Possible data race during write of size 4 at 0xADCBFB0 by thread #1
==212772== Locks held: 1, at address 0x6B8F260
==212772==    at 0x8AC3EFF: simple_mtx_destroy (simple_mtx.h:97)
==212772==    by 0x8ACB24D: intel_ds_device_fini (intel_driver_ds.cc:603)
==212772==    by 0x6CBD4D4: anv_device_utrace_finish (anv_utrace.c:471)
==212772==    by 0x6C71577: anv_DestroyDevice (anv_device.c:3679)
==212772==    by 0x6B2F1E2: loader_layer_destroy_device (loader.c:4358)
==212772==    by 0x6B3F10B: vkDestroyDevice (trampoline.c:983)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cc5843a573 ("anv: implement u_trace support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10010
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25805>
2023-10-19 09:45:36 +00:00
Lionel Landwerlin 9bea6e02b8 anv: don't uninitialize bvh_bo_pool is not initialized
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3e8d2617e1 ("anv: use buffer pools for BVH build buffers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10009
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25802>
2023-10-19 08:40:22 +00:00
Eric Anholt 20284af29b ci/iris: Drop parallel on kbl piglit to 2.
We have only 6 of these boards since one died in May, and 7 jobs allocated
to them.  So you ended up with a 5 minute delay on each pipeline with an
otherwise-idle farm while you waited for the first batch of jobs to
complete so you could get the last one started.  It turns out that piglit
was taking 3 minutes of runtime each, so we can just shard piglit 2 ways,
stay under runtime, and not over-allocate the farm

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25790>
2023-10-19 07:42:16 +00:00
Samuel Pitoiset 6cfb40a338 ci: bump DEQP_FRACTION for some jobs
Otherwise it can't complete in a reasonable amount of time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25476>
2023-10-18 12:52:37 +00:00
Samuel Pitoiset ef0997baf1 ci: update CTS to vulkan-cts-1.3.7.0
This contains many new tests, especially shader object tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25476>
2023-10-18 12:52:37 +00:00
Lionel Landwerlin 53a4738eb1 anv: track render targets & render area changes separately
The following instructions :
   - 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
   - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
   - 3DSTATE_SCISSOR_STATE_POINTERS

do not care about the content/format/count of the render targets, only
the size of the render area and count of viewport/scissor.

By tracking render targets & render area we can reduce the emission of
those instructions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25778>
2023-10-18 13:43:51 +03:00
Lionel Landwerlin c0b6ce0aac anv: reuse local variable for gfx state
No functional change.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25778>
2023-10-18 13:43:48 +03:00
Felix DeGrood b561bcd78c anv: set ComputeMode.PixelAsyncComputeThreadLimit = 4
Heuristic-based optimization throttling CCS work (async compute).
Without throttling, background compute work consumes all threads,
deminishing performance gains by running dispatch in parallel with
3D work.

Optimization is heuristics based, meaning a workload might slow
down when using async compute.

Best value: PixelAsyncComputeThreadLimit = 4. On DG2, this
equates to a max CCS thread occupancy of 37.5%.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25508>
2023-10-17 18:09:29 +00:00
Rohan Garg b94b784492 anv: fix debug string for PC flush
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Fixes: fc5cb54 ('anv: Add debug messages for DEBUG_PIPE_CONTROL')
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25690>
2023-10-17 14:31:16 +00:00
Lionel Landwerlin b207608995 intel/ds: provide names for different events of a timeline's row
Previously all items on a timeline row would have the same name. This
change uses the tracepoint names to put into the timeline instead.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25730>
2023-10-17 11:19:13 +00:00
Lionel Landwerlin 1afc876afd u_trace: generate tracepoint index parameter in perfetto callbacks
Useful to figure out what's the tracepoint name you're implementing.
We'll use this in the intel perfetto integration glue to index into an
array of perfetto iid.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25730>
2023-10-17 11:19:13 +00:00
Hyunjun Ko 960441d5a3 anv: don't flush_llc on gen9
Fixes: 3d993e63bb ("anv: Enable barrier handling on video engines ")
Closes: mesa/mesa#9988

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25762>
2023-10-17 12:28:06 +02:00
Dave Airlie d6613deed9 intel-clc: avoid using spirv-linker.
There is not real need to use the spirv-linker here at all,
we can just read all the CL C files into one buffer, then compile
that buffer in a single pass.

This worksaround an issue seen with llvm17 and opaque pointers
and the spirv linker.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25759>
2023-10-17 13:53:52 +10:00
Iván Briano abf5eb5753 anv: advertise VK_KHR_global_priority_queue
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25758>
2023-10-16 23:39:58 +00:00
Lionel Landwerlin f900b763b1 anv: workaround Gfx11 with optimized state emission
No real explanation so far.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9781
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25750>
2023-10-16 19:48:28 +00:00
Chia-I Wu 29e2e9290b anv: add support for vk_require_astc driconf
When vk_require_astc is true and there is no native ASTC LDR support,
enable ASTC LDR emulation.

vk_require_astc defaults to true on Android 14+.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25467>
2023-10-14 02:36:40 +00:00
Chia-I Wu b30d5a4794 anv: advertise emulated formats
Advertise required features for emulated formats.

v2: no sparse residency support

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25467>
2023-10-14 02:36:40 +00:00
Chia-I Wu 8352b61ffa anv: fix up blit src for emulated formats
When the blit src has an emulated format, redirect to the hidden plane.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25467>
2023-10-14 02:36:40 +00:00
Chia-I Wu 7b84c8d6ea anv: fix up image views for emulated formats
When the view format is the same as the image format, and the format is
emulated, change the format to the decompressed format.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25467>
2023-10-14 02:36:40 +00:00
Chia-I Wu a73e0e9a04 anv: decompress on upload for emulated formats
Add anv_astc_emu_decompress to decompress the raw texel data to the
hidden plane.  Call anv_astc_emu_decompress from anv_CmdCopyImage2 and
anv_CmdCopyBufferToImage2.

v2: support transfer queue and add missing flushes (Lionel)

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25467>
2023-10-14 02:36:40 +00:00
Chia-I Wu 61e480cb54 anv: add a hidden plane for emulated formats
When an image is created with an emulated format, add a hidden plane to
the image.  The hidden plane will be used for decompressed data.

v2: assert no sparse residency

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25467>
2023-10-14 02:36:40 +00:00
Chia-I Wu 9ffe8b9235 anv: add anv_is_format_emulated
anv_is_format_emulated returns true when a format is emulated.  It will
be used for ASTC LDR emulation, but it always return false at the
moment.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25467>
2023-10-14 02:36:40 +00:00