Lionel Landwerlin 11b4c23d19 anv: add ring buffer mode to generated draw optimization ...

When the number of draw calls is very large, instead of allocating
large amounts of batch buffer space for the draws, use a ring buffer
and process the draw calls by batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8645
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361>

2023-10-20 13:07:53 +00:00

..

blorp

blorp: Use the correct miptail start LOD for surfaces

2023-10-13 21:58:59 +00:00

ci

anv: uninitialize queues before utrace

2023-10-19 09:45:36 +00:00

common

intel/common: Add sse2_args for 32-bit build when -Dsse2=false was set

2023-09-15 17:39:55 -07:00

compiler

intel-clc: avoid using spirv-linker.

2023-10-17 13:53:52 +10:00

dev

intel: Sync xe_drm.h

2023-09-13 16:38:15 +00:00

ds

intel/ds: provide names for different events of a timeline's row

2023-10-17 11:19:13 +00:00

genxml

anv: enable FCV for Gen12.5

2023-10-11 12:18:15 +00:00

isl

isl: Use 16-bit instead of 8-bits for surface format info fields

2023-10-02 17:24:33 +00:00

nullhw-layer

meson: support installation tags

2023-09-11 13:00:45 +00:00

perf

intel: Move i915_drm.h specific code from common/intel_gem.h to common/i915/intel_gem.h

2023-07-28 15:36:52 +00:00

tools

intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c

2023-09-06 01:39:53 +00:00

vulkan

anv: add ring buffer mode to generated draw optimization

2023-10-20 13:07:53 +00:00

vulkan_hasvk

hasvk: Use the common GetPhysicalDeviceFeatures2 implementation

2023-09-27 23:02:29 +00:00

meson.build

intel: Only build perf if drivers or tools are enabled

2023-08-31 21:53:19 +00:00