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199591 Commits

Author SHA1 Message Date
Emma Anholt 9e145f33cb ir3: Drop old comment about ldg vectorization limitation. 
We've looked at it again, and concluded that there's just no way that LDG
crossing a boundary could be OK in the components-are-read case but bad in
the components-are-not-read case, and this must have been papering over
something else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38704>
 2025-12-04 17:18:50 +00:00
Emma Anholt 24cd5088ca ir3: Perform vectorization on ldg/stg just like other memory access. 
shader-db effect comes from (perhaps older vkd3d?) DX12 fossils.  It sure
cleans up BDA CTS testcases, too.

Totals:
MaxWaves: 22151808 -> 22485222 (+1.51%); split: +1.51%, -0.06%
Instrs: 397754007 -> 396485642 (-0.32%); split: -0.41%, +0.10%
CodeSize: 990135656 -> 916286528 (-7.46%); split: -7.64%, +0.00%
STPs: 234296 -> 218861 (-6.59%); split: -6.62%, +0.03%
LDPs: 171664 -> 155386 (-9.48%); split: -9.53%, +0.04%

Totals from 130513 (8.36% of 1560788) affected shaders:
MaxWaves: 1376826 -> 1710240 (+24.22%); split: +24.30%, -0.90%
Instrs: 57789492 -> 56521127 (-2.19%); split: -2.84%, +0.66%
CodeSize: 256430400 -> 182581272 (-28.80%); split: -29.51%, +0.01%
NOPs: 7619148 -> 8015627 (+5.20%); split: -2.42%, +7.79%
MOVs: 4971200 -> 3968352 (-20.17%); split: -21.62%, +1.37%
COVs: 683166 -> 661427 (-3.18%); split: -3.24%, +0.04%
Full: 2422659 -> 1886993 (-22.11%); split: -22.98%, +0.03%
(ss): 1410724 -> 1479394 (+4.87%); split: -3.24%, +8.43%
(sy): 611391 -> 674588 (+10.34%); split: -1.14%, +11.66%
(ss)-stall: 4930898 -> 5265129 (+6.78%); split: -3.37%, +10.29%
(sy)-stall: 24138107 -> 29357000 (+21.62%); split: -1.82%, +23.71%
STPs: 112159 -> 96724 (-13.76%); split: -13.83%, +0.07%
LDPs: 113355 -> 97077 (-14.36%); split: -14.43%, +0.07%
Preamble Instrs: 83269073 -> 46493442 (-44.16%); split: -45.32%, +0.01%
Early Preamble: 79 -> 87 (+10.13%)
Cat0: 8516132 -> 8878083 (+4.25%); split: -2.28%, +6.68%
Cat1: 5994766 -> 4973985 (-17.03%); split: -19.02%, +1.94%
Cat2: 22297064 -> 22240177 (-0.26%); split: -0.30%, +0.05%
Cat3: 13748284 -> 13748279 (-0.00%)
Cat6: 1337948 -> 780266 (-41.68%); split: -42.19%, +0.27%
Cat7: 3247729 -> 3252768 (+0.16%); split: -1.48%, +1.71%
Subgroup size: 9280960 -> 9524224 (+2.62%); split: +2.63%, -0.01%

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38704>
 2025-12-04 17:18:49 +00:00
Yogesh Mohan Marimuthu f27b2b8d77 winsys/amdgpu,ac: get eop and csa size,alignment from kernel query 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:21 +00:00
Yogesh Mohan Marimuthu f322bc8631 ac: update amdgpu_drm.h for uq metadata query info 
struct drm_amdgpu_info_uq_fw_areas is renamed to drm_amdgpu_info_uq_metadata.
query infor structure for compute and sdma is added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:20 +00:00
Samuel Pitoiset b13003133d radv: add radv_cmd_state::emitted_rt_pipeline 
To stop abusing emitted_compute_pipeline for RT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset 7d4c49a271 radv: decouple RT and compute dispatches paths 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset fa225de793 radv: constify radv_gfx12_emit_buffered_regs() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:00 +00:00
Samuel Pitoiset e3aac0d11f radv: remove redundant buffered regs emission for dispatches on GFX12+ 
It's already called few lines above.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:00 +00:00
Samuel Pitoiset 069f60a4e7 radv: enable conservativeRasterizationPostDepthCoverage on GFX10+ when possible 
This seems to work just fine, except on NAVI21, NAVI22 and VANGOGH. It
might be the same issue as has_vrs_ds_export_bug but it's not documented
anywhere. That being said, the CTS tests that fail don't even export
depth or stencil from fragment shaders.

Do not enable this feature on these GPUs to be conservative.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38767>
 2025-12-04 14:16:15 +00:00
Samuel Pitoiset d1386e167e radv: add support for computeDerivativeGroupQuads on < GFX12 
This was also supported by PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38771>
 2025-12-04 13:56:47 +00:00
Christian Gmeiner 6a8460297a lavapipe: Advertise variableMultisampleRate 
Everything is in place to support this feature already.

Passes:
 dEQP-VK.pipeline.pipeline_library.multisample.variable_rate.*

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38693>
 2025-12-04 10:33:53 +00:00
Karol Herbst a255e2ca56 nir: add ACCESS to shared_uniform_block_intel 
intel_nir_blockify_uniform_loads simply overwrites the intrinsic for
load_shared, which leads to messed up indicies, e.g:
  "base=0, access=volatile, align_mul=4, align_offset=0
became:
  "base=0, align_mul=4, align_offset=4"

Fixes: 0dd09a292b ("nir: add ACCESS_ATOMIC")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38801>
 2025-12-04 10:01:52 +00:00
Icenowy Zheng 46b97da60b pvr: fix PVR_DEBUG=info when running w/o KHR_display 
When running w/o KHR_display enabled, the display device node won't be
initlaized, and the information dump routine will terminate because of
this.

Fix this by not bailing out and not trying to print display device
compatible strings.

Fixes: 8825c91dcb ("pvr: Make display node optional")
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38787>
 2025-12-04 07:27:55 +00:00
Pavel Ondračka 1642781673 r300/ci: update expectations 
Fallout from 60e115dedf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38797>
 2025-12-04 05:50:10 +00:00
Timothy Arceri b75cd07265 util/driconf: add Cursemark workaround 
Fixes gpu hang on radeonsi and corrupt rendering on iris.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14392
Cc: mesa-stable

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38777>
 2025-12-03 23:58:15 +00:00
Connor Abbott d5498240ac spirv: Remove view_index_is_input 
The last user was removed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38793>
 2025-12-03 22:52:29 +00:00
Connor Abbott 63a38b945d tu: Call nir_lower_sysvals_to_varyings once 
Remove the early call to nir_lower_sysvals_to_varyings. This guarantees
that we only call it after lower_system_values has replaced the
variables with intrinsics. It turns out that a sequence like this
doesn't work:

1. shader declares Layer builtin as a signed integer
2. nir_lower_sysvals_to_varyings turns it into a varying (but keeps the
  signed integer type)
3. nir_lower_input_attachments (or some other pass) creates a
  nir_load_layer_id intrinsic.
4. nir_lower_sysvals_to_varyings is called again, and when creating the
  varying variable it passes an unsigned type to
  nir_get_variable_with_location(), which asserts because there is
  already a signed integer variable.

By making lower_sysvals_to_varyings happen late for layer, we can avoid
this happening by lowering away the variable before (2).

Fixes: 5bbbf5cf9b ("tu: Set use_layer_id_sysval for nir_lower_input_attachments")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38793>
 2025-12-03 22:52:29 +00:00
Connor Abbott 4cfa188db6 tu: Stop setting view_index_is_input 
glslang apparently emits ViewID as a signed integer. If other passes
generate a sysval then lower_sysvals_to_varyings() tries to create an
variable with unsigned type and asserts when the preexisting varying's
type doesn't match the type it expects. Just make ViewID a sysval and
lower it in lower_sysvals_to_varyings() to avoid this and simplify the
SPIR-V parser.

Fixes: 5bbbf5cf9b ("tu: Set use_layer_id_sysval for nir_lower_input_attachments")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38793>
 2025-12-03 22:52:28 +00:00
Marek Olšák e14f8ee0e4 nir/has_divergent_loop: require divergence metadata, check all function impls 
instead of forcing callers to call nir_divergence_analysis

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38597>
 2025-12-03 20:14:18 +00:00
Faith Ekstrand d0b83dd7ce pan: Move pan_compile_shader to pan_compiler.c 
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:45 +00:00
Faith Ekstrand e64736fba7 pan: Drop bifrost_shader_blend_info::format 
It existed entirey to save us a switch statement.  It's very unlikely
that's worth pulling GENX API command stream stuff into the compiler.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:45 +00:00
Faith Ekstrand 3970548556 pan: Move PRINTF_BUFFER_SIZE to the compiler 
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:44 +00:00
Faith Ekstrand 83f90b0760 pan/bi: Fix LD_VAR_BUF indirect offset calculations 
We multiply by 16 correctly but then drop that in the case where vbase
is non-zero.  We typically lower FS input indirects so we don't see this
often but there are a few cases where they still sneak through.

Fixes: 0fcddd4d2c ("pan/bi: Rework varying linking on Valhall")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:44 +00:00
Faith Ekstrand 9f173bb066 panvk/jm: Delete panvk_varying_hw_format() 
It's duplicated in panvk_vX_shader.c, which is where it's actually used.
This version is a dead artifact of the past.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:44 +00:00
Faith Ekstrand cad5fb4370 pan/blend: Use flat inputs for blend shaders 
There's nothing to interpolate here so there's no reason to use
nir_load_interpolated_input.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:44 +00:00
Faith Ekstrand bdd4bea636 pan/genxml: Decode blend shaders on CSF 
In order to decode blend shaders, we need to pass in the fragment binary
address because the blend pointer uses the same top 32 bits as the
fragment binary.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:43 +00:00
Gurchetan Singh 4f45e834ae gfxstream: fix logspam in TLS helper function 
Logspam has been reported in a gfxstream initialization
path.

Fixes: 4a30c6fd70 ("gfxstream: Use the Mesa common tss_* TLS helper functions")
Cc: mesa-stable

Reviewed-by: David Gilhooley <djgilhooley.gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38776>
 2025-12-03 09:12:21 -08:00
Thong Thai 4f4745ebf3 frontends/va: get libva api version from va_version.h 
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38773>
 2025-12-03 16:01:38 +00:00
Samuel Pitoiset ac37885fc8 vulkan: update spec to 1.4.335 
This renames rayTracingInvocationReorder because both NV and EXT use
the same name.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38779>
 2025-12-03 14:47:00 +00:00
Marek Olšák 9b011a7344 amd: rename most GFX115x definitions for released chips 
addrlib changes match the original code.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38718>
 2025-12-03 13:29:07 +00:00
Gil Pedersen 858364be71 intel: Add PIPE_FORMAT_R10G10B10X2_UNORM support 
This utilizes the RGBX format faking logic from e8cd7a30 to enable
PIPE_FORMAT_R10G10B10X2_UNORM renderer support using swizzling.

This format is needed for better HDR rendering support in the iris driver, to
support the Proton / Wine DXGI implementation, which requires an RGBA ordered
renderer for its Vulkan implementation. This in turn requires the Wayland
display to support both alpha and opaque formats. The check currently fails,
since only PIPE_FORMAT_R10G10B10A2_UNORM is exposed when Gallium (iris) is
the DRI Wayland renderer.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38616>
 2025-12-03 11:22:38 +00:00
Peyton Lee 3652b29573 radeonsi/vpe: correct tone mapping parameters 
Video post-processing now supports explicit color standards.
Applications can pass different combinations of primaries,
transfer functions, and color matrices.

This is used to ensure correct mapping.

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38764>
 2025-12-03 10:34:41 +00:00
Aitor Camacho df19ec3020 vulkan/wsi: Fix double destroy of present_id_timeline at swapchain create 
Fixes: c888da3d48 ("vulkan/wsi: Add mechanism to wait for WSI semaphore unsignal.")

Reviewed-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38754>
 2025-12-03 09:53:42 +00:00
Samuel Pitoiset fda1262eed radv: reduce maxTexelBufferElements to 1<<29 
It's the number of elements. RADV exposes VK_FORMAT_R64_{UINT,SINT}
formats for texel buffers, so the maximum is 1<<29 to fit in the
32-bit bounds checking.

Fixes KHR-GL46.texture_buffer_size_clamping.* with Zink and new VKCTS
dEQP-VK.texture.misc.max_elements.*.

Cc: mesa-stable.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38140>
 2025-12-03 09:31:08 +00:00
Yiwei Zhang bb19e30e0d venus: add VK_EXT_mesh_shader support 
This fills in the last piece for vkd3d-proton feature level 12_2.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38739>
 2025-12-03 07:21:53 +00:00
Yiwei Zhang 6fb6a740d9 venus: sync protocol for VK_EXT_mesh_shader support 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38739>
 2025-12-03 07:21:53 +00:00
Lionel Landwerlin 86419dd519 brw: remove driver specific load_num_workgroup lowering 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38735>
 2025-12-02 22:44:05 +00:00
Lionel Landwerlin 578d2f0daa anv: move load_num_workgroups tracking to driver 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38735>
 2025-12-02 22:44:04 +00:00
Lionel Landwerlin e12e7e117c iris: lower load_num_workgroups 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38735>
 2025-12-02 22:44:03 +00:00
Calder Young 5bf3546cc6 anv: Use companion cmd buffer for CCS and MCS image barriers 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37627>
 2025-12-02 22:22:24 +00:00
Calder Young 69f6966ae2 anv: Add shorthand for executing on the companion cmd buffer 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37627>
 2025-12-02 22:22:24 +00:00
Calder Young fe0aed2302 anv: Fix missing const qualifiers on some params in anv_blorp.c 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37627>
 2025-12-02 22:22:24 +00:00
Ian Romanick b16c169b6d vc4: Don't call nir_lower_flrp in vc4_optimize_nir 
It's already called by st_nir_opts, so it shouldn't be necessary to do
it again here.

This is only compile tested.  I have not collected any shader-db or
fossil-db data.

Acked-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12526>
 2025-12-02 21:28:05 +00:00
Ian Romanick 956a09b990 broadcom/compiler: only lower flrp once 
This is only compile tested.  I have not collected any shader-db or
fossil-db data.

v2: Drop the calls to nir_opt_constant_folding. The builder in
nir_lower_flrp will already take care of this.

v3: NIR_PASS_V is gone. Noticed by Marge.

Acked-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12526>
 2025-12-02 21:28:05 +00:00
Ian Romanick d64ce23b08 elk: only lower flrp once 
No shader-db changes on any Intel platform. Both Iris and Crocus use
st_nir_opts, which calls nir_lower_flrp before brw_nir_optimize. The
call still needs to exist for hasvk, but I don't collect fossil-db data
for hasvk.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12526>
 2025-12-02 21:28:05 +00:00
Alyssa Rosenzweig e4b8b758b1 brw: only lower flrp once 
No shader-db changes on any Intel platform.

fossil-db:

Lunar Lake
Totals:
Instrs: 926275147 -> 926273376 (-0.00%); split: -0.00%, +0.00%
Cycle count: 106012190597 -> 106011255305 (-0.00%); split: -0.00%, +0.00%
Spill count: 3424180 -> 3424168 (-0.00%)
Fill count: 4877035 -> 4877017 (-0.00%)
Max live registers: 193918196 -> 193918122 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 49106544 -> 49106448 (-0.00%); split: +0.00%, -0.00%
Non SSA regs after NIR: 231281721 -> 231281719 (-0.00%)

Totals from 1705 (0.08% of 2020028) affected shaders:
Instrs: 926974 -> 925203 (-0.19%); split: -0.28%, +0.09%
Cycle count: 39024288 -> 38088996 (-2.40%); split: -2.77%, +0.37%
Spill count: 2229 -> 2217 (-0.54%)
Fill count: 2977 -> 2959 (-0.60%)
Max live registers: 183056 -> 182982 (-0.04%); split: -0.20%, +0.16%
Max dispatch width: 46880 -> 46784 (-0.20%); split: +0.07%, -0.27%
Non SSA regs after NIR: 263520 -> 263518 (-0.00%)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12526>
 2025-12-02 21:28:05 +00:00
Ian Romanick 92e609f4fe glsl: Move flrp lowering out of the loop 
Other lower_flrp Intel platforms had similar shader-db changes.

Lunar Lake
total instructions in shared programs: 17131619 -> 17131182 (<.01%)
instructions in affected programs: 59924 -> 59487 (-0.73%)
helped: 255 / HURT: 9

total loops in shared programs: 5336 -> 5334 (-0.04%)
loops in affected programs: 4 -> 2 (-50.00%)
helped: 2 / HURT: 0

total cycles in shared programs: 888274988 -> 888269628 (<.01%)
cycles in affected programs: 1753370 -> 1748010 (-0.31%)
helped: 182 / HURT: 94

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12526>
 2025-12-02 21:28:05 +00:00
Ian Romanick 4bbc29373a nir/lower_flrp: Check and set shader_info::flrp_lowered 
No shader-db or fossil-db changes on any Intel platform.

v2: Return early if lowering_mask is zero. If the first call to
nir_lower_flrp has a lowering_mask of zero, later calls with non-zero
masks would not do any lowering. lp_bld_nir.c has this issue.

Suggested-by: Alyssa
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12526>
 2025-12-02 21:28:05 +00:00
Ian Romanick 341e2d3283 lavapipe: fp16 flrp must also be lowered 
Prevents failures with fp16 in lavapipe and Zink on lavapipe when
"nir/lower_flrp: Check and set shader_info::flrp_lowered" is
applied. Lowering with an incomplete mask on the first call to
nir_lower_flrp will prevent later calls (with the complete mask) from
doing anything.

Fixes: b38879f8c5 ("vallium: initial import of the vulkan frontend")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12526>
 2025-12-02 21:28:05 +00:00
Faith Ekstrand f1debfccaf pan: Move pan_shader_compile() to pan_compiler.h 
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38753>
 2025-12-02 21:00:30 +00:00