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14166 Commits

Author SHA1 Message Date
Georg Lehmann
9da23499ff compiler: add float8 glsl types 
e4m3fn: 8bit floating point format with 4bit exponent, 3bit mantissa
        and no infinities (finite only)
e5m2:   8bit floating point format with 5bit exponent, 2bit mantissa
        and with infinities.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35434>
 2025-06-23 07:59:24 +00:00
Lionel Landwerlin
4e25a4ce1e intel/ci: document a couple of vkd3d failures 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35679>
 2025-06-23 05:45:25 +00:00
Lionel Landwerlin
786bace191 anv: fix sampler hashing in set layouts 
The logic needs to handle embedded samplers without conversion state.

Fixes vkd3d-proton's test_sampler_border_color

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35679>
 2025-06-23 05:45:25 +00:00
Lionel Landwerlin
32b53a7c6a anv: fix clears on single aspect of YCbCr images 
Fixes vkd3d-proton's test_planar_video_formats

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35679>
 2025-06-23 05:45:25 +00:00
Lionel Landwerlin
691ac65000 isl: handle DISABLE_AUX in get_mcs_surf 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35679>
 2025-06-23 05:45:24 +00:00
Yiwei Zhang
64326d0be5 anv: use common vk_android_get_front_buffer_usage helper 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35568>
 2025-06-23 00:46:42 +00:00
Rohan Garg
e103afe7be brw: run the nir_opt_offsets pass and set the maximum offset size 
Perf A/B testing on DG2: no changes
Perf A/B testing on BMG: +2.1% Blackops3, +1.5% Cyberpunk

DG2 stats (mostly insignificant):
Assassins Creed Valhalla:
 Totals from 1169 (55.67% of 2100) affected shaders:
 Instrs: 509237 -> 509215 (-0.00%)
 Cycle count: 30614325 -> 30607419 (-0.02%); split: -0.03%, +0.00%
 Non SSA regs after NIR: 83434 -> 85909 (+2.97%)

Blackops 3:
 Totals from 1045 (64.63% of 1617) affected shaders:
 Instrs: 527312 -> 527310 (-0.00%)
 Cycle count: 496912222 -> 496902846 (-0.00%); split: -0.00%, +0.00%
 Non SSA regs after NIR: 106883 -> 109095 (+2.07%)

Cyberpunk:
 Totals from 706 (56.03% of 1260) affected shaders:
 Instrs: 345976 -> 345974 (-0.00%); split: -0.00%, +0.00%
 Cycle count: 9775138 -> 9775472 (+0.00%); split: -0.00%, +0.00%
 Max live registers: 40295 -> 40297 (+0.00%)
 Non SSA regs after NIR: 93245 -> 94718 (+1.58%)

Fortnite:
 Totals from 4210 (55.98% of 7521) affected shaders:
 Instrs: 2205471 -> 2205469 (-0.00%)
 Cycle count: 91451040 -> 91450956 (-0.00%); split: -0.00%, +0.00%
 Non SSA regs after NIR: 952354 -> 961664 (+0.98%)

LNL stats (notable changes):
Assassins Creed Valhalla:
 Totals from 1684 (83.57% of 2015) affected shaders:
 Instrs: 774305 -> 764501 (-1.27%); split: -1.27%, +0.01%
 Cycle count: 58845842 -> 58699250 (-0.25%); split: -0.98%, +0.73%
 Spill count: 625 -> 638 (+2.08%)
 Fill count: 1490 -> 1503 (+0.87%)
 Scratch Memory Size: 41984 -> 44032 (+4.88%)
 Max live registers: 196424 -> 197561 (+0.58%); split: -0.10%, +0.68%

Blackops 3:
 Totals from 1125 (76.53% of 1470) affected shaders:
 Instrs: 781749 -> 773275 (-1.08%); split: -1.08%, +0.00%
 Subgroup size: 22896 -> 22912 (+0.07%)
 Cycle count: 659864454 -> 654641032 (-0.79%); split: -1.10%, +0.31%
 Max live registers: 116772 -> 116854 (+0.07%); split: -0.01%, +0.08%
 Non SSA regs after NIR: 172648 -> 168260 (-2.54%); split: -2.55%, +0.01%

Control:
 Totals from 378 (51.50% of 734) affected shaders:
 Instrs: 148184 -> 147544 (-0.43%)
 Cycle count: 6905200 -> 6913366 (+0.12%); split: -0.30%, +0.42%
 Max live registers: 41271 -> 41281 (+0.02%)
 Non SSA regs after NIR: 44964 -> 43868 (-2.44%); split: -2.45%, +0.01%

Cyberpunk:
 Totals from 1141 (92.46% of 1234) affected shaders:
 Instrs: 636744 -> 629333 (-1.16%)
 Subgroup size: 24256 -> 24272 (+0.07%)
 Cycle count: 24952258 -> 24801298 (-0.60%); split: -1.39%, +0.78%
 Max live registers: 125848 -> 126855 (+0.80%); split: -0.00%, +0.80%
 Non SSA regs after NIR: 127399 -> 119837 (-5.94%); split: -5.95%, +0.02%

Fortnite:
 Totals from 5497 (83.52% of 6582) affected shaders:
 Instrs: 4072831 -> 4041852 (-0.76%); split: -0.77%, +0.01%
 Subgroup size: 103296 -> 103312 (+0.02%)
 Cycle count: 133046874 -> 132789242 (-0.19%); split: -0.67%, +0.48%
 Spill count: 7218 -> 7254 (+0.50%); split: -0.33%, +0.83%
 Fill count: 11724 -> 11749 (+0.21%); split: -0.34%, +0.55%
 Scratch Memory Size: 591872 -> 599040 (+1.21%)
 Max live registers: 816530 -> 818522 (+0.24%); split: -0.01%, +0.26%
 Non SSA regs after NIR: 1610296 -> 1560284 (-3.11%); split: -3.11%, +0.00%

Hitman3:
 Totals from 4713 (92.39% of 5101) affected shaders:
 Instrs: 2731598 -> 2698224 (-1.22%)
 Cycle count: 186422098 -> 185472640 (-0.51%); split: -1.12%, +0.61%
 Spill count: 3244 -> 3242 (-0.06%)
 Fill count: 9937 -> 9933 (-0.04%)
 Max live registers: 585035 -> 589801 (+0.81%); split: -0.00%, +0.82%
 Non SSA regs after NIR: 347681 -> 324314 (-6.72%); split: -6.73%, +0.01%

Hogwarts Legacy:
 Totals from 930 (59.81% of 1555) affected shaders:
 Instrs: 464146 -> 459526 (-1.00%); split: -1.00%, +0.01%
 Subgroup size: 19104 -> 19120 (+0.08%)
 Cycle count: 24062460 -> 24078964 (+0.07%); split: -0.49%, +0.56%
 Spill count: 2068 -> 1964 (-5.03%); split: -5.22%, +0.19%
 Fill count: 2342 -> 2205 (-5.85%); split: -6.40%, +0.56%
 Scratch Memory Size: 147456 -> 141312 (-4.17%)
 Max live registers: 112384 -> 112787 (+0.36%); split: -0.08%, +0.44%
 Non SSA regs after NIR: 80293 -> 79161 (-1.41%); split: -1.72%, +0.32%

Metro Exodus:
 Totals from 29755 (78.62% of 37846) affected shaders:
 Instrs: 11495578 -> 11492951 (-0.02%); split: -0.02%, +0.00%
 Subgroup size: 644688 -> 644704 (+0.00%)
 Cycle count: 301572068 -> 301548054 (-0.01%); split: -0.03%, +0.02%
 Max live registers: 3369504 -> 3370454 (+0.03%); split: -0.00%, +0.03%
 Non SSA regs after NIR: 2476561 -> 2396090 (-3.25%); split: -3.27%, +0.02%

Red Dead Redemption 2:
 Totals from 4161 (78.61% of 5293) affected shaders:
 Instrs: 2428782 -> 2409032 (-0.81%); split: -0.82%, +0.00%
 Subgroup size: 85344 -> 85360 (+0.02%)
 Cycle count: 8514984142 -> 8533415324 (+0.22%); split: -0.02%, +0.23%
 Spill count: 4659 -> 4674 (+0.32%); split: -0.02%, +0.34%
 Fill count: 11236 -> 11231 (-0.04%); split: -0.19%, +0.14%
 Scratch Memory Size: 398336 -> 397312 (-0.26%)
 Max live registers: 473946 -> 475798 (+0.39%); split: -0.08%, +0.47%
 Non SSA regs after NIR: 616820 -> 567706 (-7.96%); split: -8.09%, +0.12%

Rise Of The Tomb Raider:
 Totals from 68 (46.58% of 146) affected shaders:
 Instrs: 28209 -> 27801 (-1.45%)
 Subgroup size: 1584 -> 1600 (+1.01%)
 Cycle count: 16182992 -> 16249364 (+0.41%); split: -0.97%, +1.38%
 Max live registers: 7320 -> 7296 (-0.33%); split: -0.38%, +0.05%
 Non SSA regs after NIR: 8438 -> 8207 (-2.74%); split: -2.82%, +0.08%

Spiderman Remastered:
 Totals from 6403 (93.87% of 6821) affected shaders:
 Instrs: 5662713 -> 5597949 (-1.14%); split: -1.28%, +0.14%
 Cycle count: 282861519016 -> 279806958122 (-1.08%); split: -1.26%, +0.18%
 Spill count: 61150 -> 60754 (-0.65%); split: -1.13%, +0.48%
 Fill count: 162597 -> 163190 (+0.36%); split: -0.84%, +1.21%
 Scratch Memory Size: 5834752 -> 5804032 (-0.53%); split: -0.70%, +0.18%
 Max live registers: 901926 -> 903820 (+0.21%); split: -0.01%, +0.22%
 Non SSA regs after NIR: 555053 -> 521016 (-6.13%); split: -6.14%, +0.01%

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Rohan Garg
8a5e062e5e brw: store the buffer offset for load/store intrinsics 
This will later be encoded by the backend into the
LSC extended descriptor message.

Reworks:
  * Sagar: Add nir_intrinsic_ssbo_atomic_swap

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Rohan Garg
0186113640 brw: encode the offset into the message descriptor for Xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Rohan Garg
937d37f0b1 brw: introduce MEMORY_LOGICAL_ADDRESS_OFFSET to encode address offsets 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Lionel Landwerlin
d5a58364b1 brw: add new helper for immediate integer register with type 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Lionel Landwerlin
16fca611d7 nir: add new intel ssbo intrinsics 
Similar to ir3 ones, to optimize offsets in the backend.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:23 +00:00
Lionel Landwerlin
ba119c73c6 intel: replace RANGE_BASE by BASE for uniform block loads 
We're not currently using RANGE_BASE and we'll use BASE for offset
optimizations on Xe2+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:23 +00:00
Lionel Landwerlin
098249ba66 brw: print descriptor & extended descriptors 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:22 +00:00
Lionel Landwerlin
87ef9aabe9 intel: fix monitor build dependencies 
Signed-off-by: Lionel Landwerlin <llandwerlin@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:21 +00:00
Eric Engestrom
6b11a53a3a meson: include VkLayer_INTEL_nullhw in the devenv 
See https://github.com/KhronosGroup/Vulkan-Loader/blob/main/docs/LoaderLayerInterface.md#linux-layer-discovery

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35650>
 2025-06-20 21:51:17 +00:00
Eric Engestrom
6addaca3d4 hasvk: only run tests on x86 (32 & 64 bit) 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13305
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35635>
 2025-06-20 19:32:18 +00:00
Nanley Chery
42ef23ecd1 intel/blorp: Don't redescribe some Tile64 clears 
We don't support redescribing Tile64 and 3D due to interleaved depth
planes.

Fixes: 312952048b ("intel/blorp: Redescribe gfx12.5 surfaces for CCS fast clears")
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35619>
 2025-06-20 13:39:20 +00:00
Valentine Burley
03b480d381 ci/intel: Fix the runner tag for Flip-hatch 
The GitLab runner tags are case sensitive, and Flip-hatch's tag was
incorrectly lowercase. This prevented jobs from being picked up
by the runner.

Also remove an outdated note, as the device now appears to be stable.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35522>
 2025-06-19 20:20:42 +00:00
Lionel Landwerlin
bfee389f0c anv: only use compressed memory types on Xe2+ 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 252cac1e5c ("anv: avoid memory type changes with INTEL_DEBUG=noccs")
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35615>
 2025-06-19 19:55:59 +00:00
Mel Henning
f7aa6ba906 vulkan: Specify library_arch in ICD files 
This should help vk-icd-loader skip libraries of the wrong bit width.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35567>
 2025-06-19 17:30:24 +00:00
Samuel Pitoiset
5ff6d9cbd8 ci: uprev vkd3d 
This adds new tests with E5B9G9R9 that uncovered a RADV bug.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35634>
 2025-06-19 14:08:52 +00:00
Emma Anholt
cd981e27f7 intel/elk: Move wpos_w setup right into nir_intrinsic_load_frag_w. 
Given that the intrinsic will be CSEed at the NIR level, we don't need to
preemptively set it up at the top of the shader.  No change in HSW shader-db.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:43 +00:00
Emma Anholt
269fbcb144 intel/elk: Use pixel_z for gl_FragCoord.z on pre-gen6. 
Unless I've seriously missed something, we have the Z in the payload
(which we can always request if we need access to it and it's not already
passed to us due other WM IZ settings).

total instructions in shared programs: 4408303 -> 4408186 (<.01%)
instructions in affected programs: 1164 -> 1047 (-10.05%)
total cycles in shared programs: 142485036 -> 142484566 (<.01%)
cycles in affected programs: 26820 -> 26350 (-1.75%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:43 +00:00
Emma Anholt
dc55b47a58 intel/elk: Move pre-gen6 smooth interpolation 1/w multiply to NIR. 
NIR catches that if you're just doing something like adding two smooth
inputs, we can do the multiply once on the result instead of on each
input.  BRW shader-db results:

total instructions in shared programs: 4409146 -> 4408303 (-0.02%)
instructions in affected programs: 800761 -> 799918 (-0.11%)
total cycles in shared programs: 143203198 -> 142485036 (-0.50%)
cycles in affected programs: 79081682 -> 78363520 (-0.91%)
total sends in shared programs: 363044 -> 363042 (<.01%)
sends in affected programs: 33 -> 31 (-6.06%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:42 +00:00
Emma Anholt
fb9b2261a1 intel/elk: Move pre-gen6 gl_FragCoord.w -> interpolation lowering to NIR. 
BRW shader-db:
total instructions in shared programs: 4409143 -> 4409146 (<.01%)
instructions in affected programs: 330 -> 333 (0.91%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:41 +00:00
Emma Anholt
17ab39fbf8 intel/elk: Fix some tabs in gen4 URB setup. 
This formatted terribly in my editor, just use spaces.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:40 +00:00
Emma Anholt
9d7a016ed1 intel/elk: Retire the global float pixel_x/y values. 
Nothing used them any more.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:40 +00:00
Emma Anholt
e1bf014b6e intel/elk: Reduce this->pixel_x/y usage in gfx4 interp setup. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:40 +00:00
Emma Anholt
241bc5da70 intel/elk: Use the pixel_coord UW x/y values for noncoherent FB reads. 
No need to force generating the float cast just to turn it back to an int.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:39 +00:00
Emma Anholt
1134cdc198 intel/elk: Lower load_frag_coord to load_{pixel_coord,frag_coord_z/w} in NIR. 
This moves some conversions to NIR that may get eliminated, and also
distinguishes gl_FragCoord.z/w loads at the shader info level so we don't
need to flag uses_src_depth/uses_src_w when only gl_FragCoord.xy get used
(as is typical).  This reduces thread payload setup on many shaders.
Also, interestingly, blorp shaders stop reserving space for z/w despite
not putting them in the payload (since PS_EXTRA isn't filled out for z/w).

HSW shader-db is noise:

total instructions in shared programs: 9942649 -> 9942997 (<.01%)
instructions in affected programs: 143167 -> 143515 (0.24%)

total cycles in shared programs: 314768862 -> 314299112 (-0.15%)
cycles in affected programs: 62951452 -> 62481702 (-0.75%)

LOST:   44
GAINED: 26

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:39 +00:00
Emma Anholt
88f1656133 intel/elk: Save the UW pixel x/y as a temp. 
This will be used for representing gl_FragCoord in NIR and reducing
payload registers pushed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:38 +00:00
Emma Anholt
5222c35924 intel/elk: Save the UW pixel x/y as a temp on gfx6+. 
This will be used for representing gl_FragCoord in NIR and reducing
payload registers pushed.

HSW results:

total instructions in shared programs: 9940636 -> 9948574 (0.08%)
instructions in affected programs: 852560 -> 860498 (0.93%)

total cycles in shared programs: 314804525 -> 314900080 (0.03%)
cycles in affected programs: 39786599 -> 39882154 (0.24%)

LOST:   5
GAINED: 11
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:38 +00:00
Emma Anholt
af74abd68c intel/fs: Don't bother checking if load_frag_coord uses interpolation. 
This was leftover dead code from 4bb6e6817e ("intel: Use a system value
for gl_FragCoord") -- the sysval doesn't do any interpolation and doesn't
have sources that could use a barycentric.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:37 +00:00
Emma Anholt
1b9b63de37 intel/shim: Report I915_PARAM_HAS_GEN7_SOL_RESET. 
Quiets more startup warnings from drm-shim.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:37 +00:00
Emma Anholt
1b6689d79e intel/shim: Report support for PXP status. 
Otherwise drm-shim complains on every shader-db run.

Fixes: e358173fbf ("iris: Add GET_PARAM for protected context capability support")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
 2025-06-18 23:11:37 +00:00
Emma Anholt
0bf114736a intel: Use the common NIR lowering for fquantize2f16. 
This generates one extra instruction to set the rounding mode to RTE due
to f2f16_rtne in the lowering.  This changes the result for
fquantize2f16(65505.0) from 65536 to 65504, which fixes SPIR-V
conformance for this value:

    If Value is positive with a magnitude too large to represent as a
    16-bit floating-point value, the result is positive infinity. If Value
    is negative with a magnitude too large to represent as a 16-bit
    floating-point value, the result is negative infinity.

SPIR-V doesn't specify whether this overflow check is before or after
rounding, but IEEE specifies rounding first, which is what produces our
65504.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25552>
 2025-06-18 22:45:08 +00:00
Yiwei Zhang
4efaa64159 vulkan/treewide: add and use common Android HMI hal implementation 
There's no need for a per driver HMI implementation since the
vk_icdGetInstanceProcAddr implementation can well populate the required
entrypoints for Android icd.

Changes have to be done in this single commit for simplicity. Otherwise,
I would have to create a separate android shared library in the runtime
like how vk_instance is handled today, so that the target is able to
check per driver enablement def. However, after all drivers have
migrated over within this MR, we still have to clean those up. So I
decided to just do those in a single commit instead.

v2: avoid preloading u_gralloc in vulkan hal open

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
 2025-06-18 22:23:53 +00:00
Yiwei Zhang
02c65181c1 hasvk: free up hwvulkan_device_t upon driver unloading 
Per <hardware/hwvulkan.h>, the hw_device_t::close() function is called
upon driver unloading. The behavior has been like this since Android 10.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
 2025-06-18 22:23:49 +00:00
Yiwei Zhang
710282f83c anv: adopt common Android gralloc helpers 
u_gralloc will be initialized upon the initial vk_android_get_ugralloc.

v2: drop explicit gralloc init

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
 2025-06-18 22:23:49 +00:00
Yiwei Zhang
896bda5143 anv: free up hwvulkan_device_t upon driver unloading 
Per <hardware/hwvulkan.h>, the hw_device_t::close() function is called
upon driver unloading. The behavior has been like this since Android 10.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
 2025-06-18 22:23:49 +00:00
Sagar Ghuge
a676ba9294 anv: Apply flush during WriteAccelerationStructures 
We are reading accel header parameter those are updated by CS, so we
need to apply flushes to make L3 coherent with CS.

This fixes ray query tests on MTL:
- dEQP-VK.ray_query.*.serialization.*

Cc: mesa-stable

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35590>
 2025-06-18 20:56:56 +00:00
José Roberto de Souza
37f4182ac3 Revert "anv: Enable preemption due 3DPRIMITIVE in GFX 12" 
Enabling preemption in 3DPRIMITIVE is causing glitches on Dota 2,
so reverting this until the issue with preemption is fixed.

This reverts commit 3cd972a2d3.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13289
Fixes: 12ddaa6b8b9e ("anv: Enable preemption due 3DPRIMITIVE in GFX 12")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35586>
 2025-06-18 18:52:19 +00:00
Valentine Burley
e82e1bca1d intel/ci: Drop deprecated fp16 environment variable 
Fixes: cf3ec8d3b9 ("rusticl: enable proper fp16 support")
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35574>
 2025-06-18 06:13:25 +00:00
Valentine Burley
04d35cacbf intel/ci: Reduce parallelism of intel-adl-cl job 
The intel-adl-cl job was previously running on two DUTs, but the
runtime reported by deqp-runner was only about 3 minutes.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35574>
 2025-06-18 06:13:25 +00:00
Valentine Burley
68244ee819 anv/ci: Add a pre-merge vkd3d job on ADL 
Introduce a new, pre-merge vkd3d-proton job on Alder Lake, and move the
VK_DRIVER variables to the .anv-test template.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35574>
 2025-06-18 06:13:25 +00:00
Yiwei Zhang
5cb50c3cf5 hasvk: use narrow range to match up with mesa EGL 
This matches up with the native gl drivers as well as the media stack.

- VK_SAMPLER_YCBCR_RANGE_ITU_NARROW <=> EGL_YUV_NARROW_RANGE_EXT

Cc: mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35597>
 2025-06-17 22:51:40 -07:00
Yiwei Zhang
c169ad60c1 anv: use narrow range to match up with mesa EGL 
This matches up with the native gl drivers as well as the media stack.

- VK_SAMPLER_YCBCR_RANGE_ITU_NARROW <=> EGL_YUV_NARROW_RANGE_EXT

Cc: mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35597>
 2025-06-17 22:51:30 -07:00
Calder Young
03cdb3078a anv: Support multi-planar formats in anv_formats_are_compatible 
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
 2025-06-17 11:23:46 +00:00
Lionel Landwerlin
f4c1753c1a anv: report color/storage features on YCbCr images with EXTENDED_USAGE 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13219
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
 2025-06-17 11:23:46 +00:00