Commit Graph

194555 Commits

Author SHA1 Message Date
Job Noorman 9b418671cf ir3: don't add array stores to block keeps
Array accesses (including stores) are fully converted to SSA. This means
ir3_dce can handle them correctly and we don't have to forcefully keep
them around.

Totals:
MaxWaves: 2381954 -> 2382720 (+0.03%)
Instrs: 49073677 -> 49056449 (-0.04%)
CodeSize: 102537524 -> 102485082 (-0.05%); split: -0.05%, +0.00%
NOPs: 8396340 -> 8405825 (+0.11%)
MOVs: 1450777 -> 1433266 (-1.21%)
COVs: 825142 -> 822678 (-0.30%)
Full: 1714304 -> 1712751 (-0.09%)
(ss): 1126433 -> 1126611 (+0.02%); split: -0.00%, +0.02%
(sy): 554174 -> 554194 (+0.00%); split: -0.00%, +0.00%
(ss)-stall: 4013834 -> 4014314 (+0.01%)
(sy)-stall: 16713036 -> 16713790 (+0.00%); split: -0.00%, +0.01%
LDPs: 23957 -> 23701 (-1.07%)
Preamble Instrs: 11106162 -> 11105987 (-0.00%)
Cat0: 9252109 -> 9261512 (+0.10%)
Cat1: 2337941 -> 2317966 (-0.85%)
Cat2: 18452467 -> 18448379 (-0.02%)
Cat3: 14099754 -> 14097262 (-0.02%)
Cat4: 1362443 -> 1362435 (-0.00%)
Cat6: 515831 -> 515767 (-0.01%)
Cat7: 1636810 -> 1636806 (-0.00%)

Totals from 417 (0.25% of 164705) affected shaders:
MaxWaves: 5552 -> 6318 (+13.80%)
Instrs: 160717 -> 143489 (-10.72%)
CodeSize: 367044 -> 314602 (-14.29%); split: -14.30%, +0.01%
NOPs: 29576 -> 39061 (+32.07%)
MOVs: 25110 -> 7599 (-69.74%)
COVs: 5276 -> 2812 (-46.70%)
Full: 6879 -> 5326 (-22.58%)
(ss): 3484 -> 3662 (+5.11%); split: -0.32%, +5.42%
(sy): 2486 -> 2506 (+0.80%); split: -0.12%, +0.93%
(ss)-stall: 8949 -> 9429 (+5.36%)
(sy)-stall: 124684 -> 125438 (+0.60%); split: -0.28%, +0.89%
LDPs: 256 -> 0 (-inf%)
Preamble Instrs: 60629 -> 60454 (-0.29%)
Cat0: 33230 -> 42633 (+28.30%)
Cat1: 30386 -> 10411 (-65.74%)
Cat2: 43140 -> 39052 (-9.48%)
Cat3: 26251 -> 23759 (-9.49%)
Cat4: 1148 -> 1140 (-0.70%)
Cat6: 102 -> 38 (-62.75%)
Cat7: 13332 -> 13328 (-0.03%)

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36720>
2025-08-13 07:05:12 +00:00
Lionel Landwerlin 9a6065852d anv: Do not consider task as prerasterization
What drivers state programming in the 3D pipeline is the mesh shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36734>
2025-08-13 06:24:44 +00:00
Lionel Landwerlin 46c16f854e brw: compute consistent clip/cull distance masks with VUE
We can optimize the VUE layout in cases where all shaders are compiled
together and some outputs are unused. So we need to have consistent
clip/cull_distance_mask with the VUE.

Previously we could have a VUE without ClipDistance present in the
header and yet have a non zero clip_distance_mask. This would trip the
HW into taking into account a VUE field that doesn't exist.

Here we set the clip/cull_distance_mask to 0 if the associated output
is not written by the shader. The written outputs are always
consistent with what's in the VUE.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2d396f6085 ("intel: prepare VUE layout for more than 2 layouts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13685
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36734>
2025-08-13 06:24:44 +00:00
Sagar Ghuge cac3b4f404 anv: Mask off excessive invocations
For unaligned invocations, don't launch two COMPUTE_WALKER, instead we
can mask off excessive invocations in the shader itself at nir level and
launch one additional workgroup.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36245>
2025-08-12 23:17:02 +00:00
Sagar Ghuge 7b634ebb63 vulkan/runtime: Add VK_SHADER_CREATE_UNALIGNED_DISPATCH_BIT_MESA flag
Drivers that doesn't support direct unaligned dispatches, they can use
the shader creation flag to lower unaligned dispatches.

Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36245>
2025-08-12 23:17:02 +00:00
Sagar Ghuge 349de5b0be anv: Use vk_get_bvh_build_pipeline_spv helper
Took inspiration from RADV driver changes. This allow us to get rid of
our local helper get_pipeline_spv().

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36245>
2025-08-12 23:17:02 +00:00
Karol Herbst 20b2944274 rusticl: silence new warnings from rustc versions above our rustc target
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36747>
2025-08-12 22:37:52 +00:00
Karol Herbst ea69a01378 rusticl: silence warnings in generated sources
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36747>
2025-08-12 22:37:52 +00:00
David Rosca 09dd2bc388 rusticl/ptr: Fix hidden lifetime warning
error: hiding a lifetime that's elided elsewhere is confusing
   --> ../src/gallium/frontends/rusticl/util/ptr.rs:166:18
    |
166 |     pub fn entry(&mut self, ptr: P) -> Entry<P, T> {
    |                  ^^^^^^^^^             ----------- the same lifetime is hidden here
    |                  |
    |                  the lifetime is elided here

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36747>
2025-08-12 22:37:52 +00:00
Faith Ekstrand 47ef0d2470 nvk: Allow kepler in nvk_is_conformant()
Thanks to "Enable X platform" patches living way too long (Vulkan
conformance has a 30 day delay), there was a little rebase fail and we
turned on Kepler and then accidentally turned it back off.

Fixes: f4b01bbfe7 ("nvk: Add an nvk_is_conformant() helper")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36745>
2025-08-12 19:50:21 +00:00
Robert Mader 3f995bf817 anv: Enable G8_B8_R8_3PLANE_422 and G8_B8_R8_3PLANE_444 formats
They are well supported and useful for efficient playback of software
decoded videos - e.g. when allocating buffers with udmabuf or dma heaps
and then importing them into Vulkan.

Signed-off-by: Robert Mader <robert.mader@posteo.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35273>
2025-08-12 19:16:29 +00:00
Sagar Ghuge ba1ddb6b62 vulkan/radix_sort: Fix subgroup invocation id
When we have single subgroup within a workgroup, I guess we want to
index invocation within the subgroup, we don't want the ID of subgroup
within local workgroup, since it will be always 0.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36733>
2025-08-12 18:39:20 +00:00
Yiwei Zhang 1abe0d38d1 vulkan/util: update common properties code gen to use platform guard
Similar to the prior feature code gen update. This one here also absorbs
the Android private ANB struct.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Yiwei Zhang 9999cd3967 vulkan/util: no need to hide ANB property itself behind Android
Property members are never going to use platform specific struct.
Getting rid of the guard around sharedImage propperty simplifies driver
side setting the prop.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Yiwei Zhang 567cff487c vulkan/util: add missing vulkan header
Unlike features, property members do need Vulkan header. Currently it
relies on the fact that vk_physical_device.h has included some other
headers that include vulkan.h before this.

Cc: mesa-stable
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Lucas Fryzek 23d7c3fbd5 vulkan/util: update pd feature codegen to use platform guards
If a given physical device feature needs a platform specific define
guard, generate the appropriate one instead of just ignoring it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Aaron Ruby 796e11008d vulkan/wsi: No commandPool allocation required for WSI_SWAPCHAIN_NO_BLIT
commandPools/cmdBuffers are only required for swapchain configurations
that use a blit-queue. They do not need to be allocated at all in the
"no blit" configuration.

There are some validUsage issues with the commandPool allocation, namely
that the WSI impl assumes that the logical device was created with all
queueFamilies made available to it. This is an invalid assumption that
can result in: VUID-vkCreateCommandPool-queueFamilyIndex-01937 invalid
usage on the eventual call to the driver. Note: invalid usage by WSI
wouldn't normally be detectable without virtualization.

This change reduces the scope of that invalid usage.

Reviewed-by: Gurchetan Singh <gurchetansingh@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36361>
2025-08-12 11:44:24 -04:00
Gert Wollny 8c65da0c9d r600/sfn: cleanup GS shader emission
Now that we lower all load_per_vertex_input to
r600_load_per_vertex_input we can remove some dead code
and also change the intrinsic to use only one source value.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:17 +00:00
Gert Wollny eccd178f0b r600/sfn: Lower all GS indirect input loads after lowering IO
Extend the lowering of indirect GS array inputs to include
all indirect access. This replaces
   r600_gs_load_deref_io_to_indirect_per_vertex_input
which was restricted to vec4 POS inputs. The
new lowering pass works in all vayings and all types, so we
can also drop the call to nir_lower_indirect_derefs.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:16 +00:00
Gert Wollny 356bc41797 r600/sfn: resolve constant indices into local arrays better
When the code is first generated constants are loaded to registers, so to
avoid indirect array register access that can be resolved as a direct direct
access we have to check whether the address register is loaded
with a constant value.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:15 +00:00
Gert Wollny 874005aeb7 r00/sfn: Fix copy propagation into buffer load address
A buffer load can not use an indirect register as address.

Fixes: 79ca456b48 ("r600/sfn: rewrite NIR backend")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:14 +00:00
Gert Wollny 39543f6b5c r600/sfn: Handle indirect access to GS input arrays
nir_intrinsic_load_per_vertex_input has two source values, indirect access
by using the first value is already handled, but accessing arrays with
the second index was missing but became relevant with handling most IO
optimizations with nir_opt_varyings.

Fixes: 37ae4df3e4 ("glsl: remove most IO optimizations that are replaced by nir_opt_varyings")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:14 +00:00
Gert Wollny 9c8d8cfa07 r600/sfn: factor out adding an input in GS
This is a preparation for the next patch that will fix
indirect access using the second index of load_per_vertex_input

Fixes: 37ae4df3e4 ("glsl: remove most IO optimizations that are replaced by nir_opt_varyings")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:13 +00:00
Derek Foreman b94add2977 dril: Skip some pipe formats to avoid breaking X
In the case where gbm fails to init, we use our entire format list. That
became a problem in commit 642c4cf2b2 when some formats were added to the
list that X can't handle. This leads to X crashing when using glx and
trying to use certain visuals.

An easily testable manifestation of this crash is to run piglit's
glx-create-context-ext-no-config-context under Xwayland in a virtual
machine that has no gpu, whilst using zink. Much like our CI does for some
jobs.

Fixes: 642c4cf2b2 ("dril: add BGR{X,A}8888 and RGB{X,A}8888")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36575>
2025-08-12 14:06:05 +00:00
Samuel Pitoiset 0d4d73a780 radv: implement an alternative workaround for HiZ on GFX12
This disables HiZ on-demand when both depth/stencil are enabled and
depth writes are enabled to prevent potential issues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:10 +00:00
Samuel Pitoiset b6a9ed48c9 radv: validate dynamic states earlier
This will be needed to emit the GFX12 alternative HIZ wa.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:10 +00:00
Samuel Pitoiset 3de108da66 radv/meta: update HiZ metadata after depth/stencil image clears
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:10 +00:00
Samuel Pitoiset e6c485afb0 radv: initialize HiZ metadata during image layout transitions
This will allow us to enable HiZ for all levels of the image.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:10 +00:00
Samuel Pitoiset 297cf6f1aa radv/meta: add a pass to clear HiZ surfaces
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:09 +00:00
Samuel Pitoiset 8886a3385b radv: add a function to create an image view for HiZ surfaces
Only for storage because that's the only use case.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:09 +00:00
Samuel Pitoiset d89922a6a8 radv: allocate image metadata to implement a workaround for HiZ on GFX12
This will be used to determine if HiZ can enabled per level.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:09 +00:00
Samuel Pitoiset a2d996b70c ac/descriptors: add a function to create a descriptor for HiZ surfaces
HiZ is a separate image using standard image layout and tiling.
No need to support HiS which isn't available in any production chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:09 +00:00
Mike Blumenkrantz c7045e3e63 perfetto: unify init
util_perfetto_init() was called in some places, util_cpu_trace_init()
was called in other places, and some places used tracing without ever
calling either of them

util_cpu_trace_init() is now guaranteed to be called:
* on gallium screen create
* on VK instance create

thus no driver/frontend/etc should ever need to call this manually

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36628>
2025-08-12 13:17:43 +00:00
Caterina Shablia f53bf77d47 panvk/csf: plop the stage and access masks into panvk_sync_scope
Stage and access masks often go together. Representing the two
with a single value lets us have neater code.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
2025-08-12 12:43:10 +00:00
Caterina Shablia 1f7af54da9 panvk: do not zero AFBC when an image is being bound
Binding an image must not write anything into the memory it's
being bound to.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
2025-08-12 12:43:10 +00:00
Caterina Shablia ed6f6c723f panvk: call cmd_transition_image_layout for each image memory barrier
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
2025-08-12 12:43:10 +00:00
Caterina Shablia c95f899305 panvk: add a meta command for transitioning image layout
Currently the only thing this function ever does is clear AFBC
metadata when transitioning away from UNDEFINED.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
2025-08-12 12:43:10 +00:00
Caterina Shablia 8e3fb838ac panvk/csf: change get_cs_deps to be add_cs_deps
Make get_cs_deps accumulate the dependencies. This is useful when
implementing layout transitions. Layout transitions away from
UNDEFINED are implemented with a compute dispatch sandwiched
in-between src and dst, specified in the image barrier. When
implementing device event wait and the event dependency needs a
layout transition, we can defer emitting the barrier that syncs
layout transition dispatches with dst until after we have emitted
all dispatches, avoiding sync between the said transition
dispatches.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
2025-08-12 12:43:10 +00:00
Caterina Shablia e6d2a426e6 vulkan/runtime: add vk_image_subresource_slice_count
vk_image_subresource_slice_count is useful when implementing image
barriers. When maintenance9 is enabled,
VkImageSubresourceRange::{baseArrayLayer,layerCount} specify the
slices, rather than layers, to transition. This helper returns
the number of slices specified in the subresource range, accounting
for the VK_REMAINING_ARRAY_LAYERS sentinel.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
2025-08-12 12:43:10 +00:00
Georg Lehmann 8818d7367d nir/opt_load_skip_helpers: optionally handle intrinsics
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
2025-08-12 08:56:37 +00:00
Georg Lehmann cd687e277f nir: add access for scratch loads
To be able to use ACCESS_SKIP_HELPERS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
2025-08-12 08:56:37 +00:00
Georg Lehmann 2d16f457c5 nir: add ACCESS_SKIP_HELPERS
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
2025-08-12 08:56:37 +00:00
Georg Lehmann 91572a99bb nir: rename to nir_opt_load_skip_helpers and add options struct
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
2025-08-12 08:56:37 +00:00
Georg Lehmann fbae0893a6 nir: print skip_helpers for tex instrs
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
2025-08-12 08:56:37 +00:00
Georg Lehmann 6577f68ad4 nir/opt_tex_skip_helpers: never require helpers for stores/atomics
Helpers never execute stores/atomics.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
2025-08-12 08:56:37 +00:00
Georg Lehmann 26e6c4c092 nir/opt_tex_skip_helpers: don't skip helpers for terminate_if source
Helpers must be terminated correctly.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
2025-08-12 08:56:37 +00:00
Samuel Pitoiset 0c9f079295 radv/amdgpu: fix creation with different but unused RADV_PERFTEST flags
This fixes an issue with Hellblade Senua's Sacrifice because
RADV_PERFTEST_RT_WAVE_64 is set using drirc, but if two devices are
created RADV_PERFTEST flags might differ.

The proposed solution is to filter out unused RADV_PERFTEST flags for
the winsys.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36727>
2025-08-12 07:46:04 +00:00
Samuel Pitoiset b2ea120732 ac,radv,radeonsi: fix programming PA_SU_PRIM_FILTER_CNTL on GFX12
GFX12 seems to behave slightly differently. Setting these bits to TRUE
causes zero-area triangles to not pass the primitive clipping stage.
So, the actual number of primitives output by the primitive clipping
stage was wrong.

After digging a lot, it seems PAL doesn't set these bits either on
GFX12.

CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36670>
2025-08-12 07:06:36 +00:00
Samuel Pitoiset f23d211b16 radv: fix destroying CS with RADV_PERFTEST=dmashaders
Typo during this huge refactor with radv_cmd_stream.

Fixes: 3ccb48ec46 ("radv: switch to radv_cmd_stream everywhere")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36706>
2025-08-12 06:48:20 +00:00
Gert Wollny 8746397461 r600/sfn: allow skipping RA for shader ID ranges
This helps identifying problems with RA when many shaders
are compiled.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36554>
2025-08-11 22:28:36 +00:00