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10953 Commits

Author SHA1 Message Date
Sviatoslav Peleshko 98665e024f intel/tools/i965_asm: Handle sync instruction 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko 9dd3a6f86f intel/tools/i965_asm: Handle HF immediates 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko 0c41a8f5d6 intel/tools/i965_asm: Add SWSB handling 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko cfb34dc695 intel/eu/validate: Validate that the ExecSize is a factor of chosen ChanOff 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko dbf6f0291a intel/fs: Set group 0 for Wa_14010017096 MOV instruction 
We always set exec size to 16 for this MOV, but the execution group remains
from the previous emitted instruction. This can cause emitting a group
which violates PRM restriction for ChanOff: "The execution size (ExecSize)
must be a factor of the chosen offset."

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko 173a991405 intel/disasm: Print src1_len correctly depending on ExDesc type 
There are two "Src1.Length" with different formats in "send" description
in the PRMs. One is part of ExMsgDesc, is relevant for LSC SFIDs, and
exists if [ExDesc.IsReg]==false. The other is just a 5-bit immediate,
is relevant for other SFIDs too, and exists if ([ExDesc.IsReg]==true)
AND ([ExBSO]==true).

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko b5c0b90402 intel/compiler: Set flag reg to 0 when disabling predication 
Having the reg set with predication disabled shouldn't cause any problems
during the execution. But when decompiling such instruction the flag won't
be shown in the output, so the recompiling will cause
functionally-identical but binary-different code. Fixing this makes
disasm/asm testing easier.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko a129e136de intel/disasm: Print half-float values instead of placeholder 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko 4f41c44df2 intel/compiler: Add variable to dump binaries of all compiled shaders 
This can be useful for testing i965_disasm and i965_asm by comparing
bin -> asm -> bin results.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
 2024-01-09 11:35:51 +00:00
Caio Oliveira ef88a20d96 intel/compiler: Use INTEL_DEBUG=cs to ask for brw_compiler output 
This removes output like

```
CS SIMD16 shader: 2790 inst, 0 loops, 24804 cycles, 166:106 spills:fills, 35 sends,
  scheduled with mode top-down, Promoted 1 constants, compacted 44640 to 41424 bytes.
```

from the default builds.  Like other debug output in intel_clc, they can
re-enabled with INTEL_DEBUG=cs.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939>
 2024-01-09 01:26:41 +00:00
Caio Oliveira c21213b438 anv: Don't print warnings for GRL kernel compilations 
Make the build less chatty.  The current warnings are about certain
capabilities not being fully supported, which we don't care for these
particular kernels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939>
 2024-01-09 01:26:41 +00:00
Lionel Landwerlin 4b30b46ffd intel/fs: fix depth compute state for unchanged depth layout 
There is no VK CTS exercising this case. If there was we would run
into hangs as noticed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26876

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26923>
 2024-01-08 17:28:12 +00:00
Lionel Landwerlin f12ffc6b04 isl: implement Wa_22015614752 
This workaround requires 64Kb alignment for compression with multiple
engine accesses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8614
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26890>
 2024-01-08 08:21:14 +00:00
Lionel Landwerlin 32450d0901 isl: further restrict alignment constraints 
We can limit the AUX-TT requirements to formats supporting CCS.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26890>
 2024-01-08 08:21:14 +00:00
Mark Janes 2236dc3481 intel/dev: update workaround definitions to latest defect status 
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:46 +00:00
Mark Janes 590fe58ef6 intel: remove MTL a0 workarounds 
Meteorlake shipped with the b0 stepping.  Remove fixes for hardware
bugs that were corrected prior to the platform release.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:46 +00:00
Mark Janes a6a95591aa intel/dev: poison macros for workarounds fixed at a stepping 
INTEL_NEEDS_WA macros are valid when a workaround applies to all
platforms which have the GFX_VERx10 versions for the workaround.

Some workarounds were fixed at a stepping after the platform release.
If a workaround applies partially to any platform, then GFX_VERx10
cannot be used to correctly apply the workaround.

This change invalidates INTEL_NEEDS_WA_16014538804 and
INTEL_NEEDS_WA_22014412737, which were fixed for MTL platforms at
stepping b0.  The run-time checks were already present for all uses of
these macros.  Updating the poisoned macros to INTEL_WA_{num}_GFX_VER
compiles out the run-time checks on platforms where they cannot apply.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:45 +00:00
Mark Janes 7354d3a947 intel/dev: improve descriptions of workaround macros. 
Instructions for INTEL_WA_{num}_GFX_VER macros were confusing and
contradicted itself.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:45 +00:00
Yonggang Luo d6c258d9ee util: Add align_uintptr and use it treewide to replace ALIGN that works on size_t and uintptr_t 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26866>
 2024-01-05 21:54:35 +00:00
Caio Oliveira 77f4f3112d intel/fs: Use linear allocator in fs_live_variables 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670>
 2024-01-04 23:06:07 +00:00
Caio Oliveira b5cd91501d intel/fs: Use linear allocator in opt_copy_propagation 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670>
 2024-01-04 23:06:07 +00:00
Caio Oliveira 6d2503e935 intel/fs: Only allocate acp_entry if we are adding one 
In practice it seems we are always entering here, haven't looked
in detail whether at this point we could just assert.  But for now
only allocate a new acp_entry if we are going to add it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670>
 2024-01-04 23:06:07 +00:00
Sagar Ghuge 96e0d979a7 intel/fs: Check fs_visitor instance before using it 
On Xe2+, we don't build the SIMD8 shader so this check makes sure we
don't execute the uninitialized invocations.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26886>
 2024-01-04 22:24:07 +00:00
Dave Airlie 56a72e014f intel/compiler: reemit boolean resolve for inverted if on gen5 
Gen5 adds some boolean conversion instructions after nir emits,
but that nir srcs don't line up with them, so reemit the boolean
conversion if we reemit the inot.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 31b5f5a51f ("nir/opt_if: Simplify if's with general conditions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26782>
 2024-01-04 21:27:23 +00:00
Dave Airlie 8f73cc802c intel/compiler: revert part of "Move earlier scheduler code that is not mode-specific" 
This removed a bunch of calls from the vec4 code that aren't called anywhere else.

Bring back the bits that were removed.

Fixes glxgears on gen5

Fixes: 81594d0db1 ("intel/compiler: Move earlier scheduler code that is not mode-specific")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26862>
 2024-01-04 00:38:38 +00:00
Dave Airlie 37366fef68 intel/compiler: fix release build unused variable. 
This is only used in an assert.

Fixes: 158ac265df ("intel/fs: Make helpers for saving/restoring instruction order")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26863>
 2024-01-03 23:52:11 +00:00
Daniel Schürmann a3ed36da1a treewide: replace calls to nir_opt_trivial_continues() with nir_opt_loop() 
Totals from 850 (1.11% of 76636) affected shaders: (RADV, GFX11)
MaxWaves: 18134 -> 18130 (-0.02%)
Instrs: 3011298 -> 3008585 (-0.09%); split: -0.17%, +0.08%
CodeSize: 15836804 -> 15841972 (+0.03%); split: -0.09%, +0.12%
VGPRs: 63580 -> 63604 (+0.04%)
SpillSGPRs: 966 -> 1148 (+18.84%); split: -0.83%, +19.67%
Latency: 36102291 -> 30186144 (-16.39%); split: -16.41%, +0.02%
InvThroughput: 9058100 -> 7011821 (-22.59%); split: -22.61%, +0.02%
VClause: 65369 -> 65364 (-0.01%); split: -0.03%, +0.02%
SClause: 100309 -> 100305 (-0.00%); split: -0.04%, +0.04%
Copies: 335658 -> 336472 (+0.24%); split: -0.70%, +0.94%
Branches: 110806 -> 108945 (-1.68%); split: -1.94%, +0.26%
PreSGPRs: 73476 -> 73934 (+0.62%); split: -0.25%, +0.87%
PreVGPRs: 58809 -> 58840 (+0.05%); split: -0.01%, +0.06%

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24940>
 2024-01-03 20:48:04 +00:00
Yonggang Luo 472b6f5379 intel,crocus,iris: Use align64 instead of ALIGN for 64 bit value parameter 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Yonggang Luo 5a2aa3ff88 intel: Cleanup duplicate ALIGN macro defines 
Use ALIGN function instead

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Yonggang Luo 8665ce27bc intel: Use ALIGN_POT instead of ALIGN inside macro define 
These macro define is compute from literals, so use ALIGN_POT instead of ALIGN function
so that it's can be computed at compile time

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Yonggang Luo 3a9c569177 intel: Avoid use align as variable, replace it with other names 
align is a function and when we want use it, the align variable will shadow it
So replace it with other names

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
 2024-01-03 12:46:10 +00:00
Mark Janes 188c349e51 intel: remove workaround for preproduction DG2 steppings 
DG2_G10 was released with stepping C0.
DG2_G11 was released with stepping B1.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26845>
 2024-01-02 16:06:37 -08:00
Iván Briano 56d556f821 anv: enable VK_KHR_maintenance6 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:02 +00:00
Iván Briano b7c4fe54cb anv: move astc_emu to use descriptors2 calls 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:02 +00:00
Iván Briano ce6899d804 anv: add support for Cmd*DescriptorSet*2KHR 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:02 +00:00
Iván Briano 40377eed91 anv: handle VkBindMemoryStatusKHR on buffer/image memory bind 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:02 +00:00
Iván Briano abe0cc8aa4 anv: remove no longer valid assert 
Maintenance6 allows creating uncompressed views of compressed images
with multiple layers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:02 +00:00
Iván Briano 3b5615500a anv: allow NULL index buffers 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
 2024-01-02 22:12:01 +00:00
Tapani Pälli fe5c82e853 isl: implement Wa_14018471104 
Set EnableSamplerRouteToLSC in case ResourceMinLOD is 0.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
José Roberto de Souza 70382f7f06 intel/isl/xe2: Enable route of Sampler LD message to LSC 
Xe2 allows route of LD messages from Sampler to LSC to improve
performance when some restrictions are met.

BSpec: 57023
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
Zhang, Jianxun e9b633619c intel/genxml: Add RENDER_SURFACE_STATE for xe2 
The indirect BO of clear color is also removed along with clear value
address and its enabling.

Other delta in struct RENDER_SURFACE_STATE are deferred to their
functional enabling changes.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
Jordan Justen db5be18862 intel/genxml/gfx125: Move STATE_SURFACE_TYPE to enum 
This will allow us to use it in Xe2 genxml.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
Jordan Justen 772ce98a81 intel/genxml/gfx125: Move L1_CACHE_CONTROL to enum 
This will allow us to use it in Xe2 genxml.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
Sagar Ghuge 9e97ce59a8 anv: No need to emit PIPELINE_SELECT on Xe2+ 
On Xe2+, PIPELINE_SELECT is getting deprecated (Bspec 55860), as a
result we don't have to do the stalling flushes while switching between
different pipelines.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26637>
 2024-01-02 20:57:33 +00:00
Ian Romanick 2e75d71c1f intel/cmat: Generate better code for nir_intrinsic_cmat_insert 
When the source destination index is a constant, we can avoid generating
a lot of the intermediate code. At the very least, this makes initial
NIR dumps much easier to read.

v2: Simplify tracking of dst_index. Suggested by Caio.

Suggested-by: Caio
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
 2023-12-29 20:28:54 -08:00
Ian Romanick c6d44284aa intel/dev: Enable VK_KHR_cooperative_matrix on all Gfx9+ GPUs 
Gfx12.5 (DG2) will use DPAS instructions to accelerate the
implementation. Earlier platforms will use equivalent discrete
instructions (basically subgroup operations). Gfx12 (Tigerlake) will use
DP4A for 8-bit integer matrix multiplication. Older platforms, which
lack DP4A, will use a suboptimal instruction sequence. There is plenty
of room for improvement here.

On DG2 (Gfx12.5) gets the following results from the CTS:

Test run totals:
  Passed:        1642/13982 (11.7%)
  Failed:        0/13982 (0.0%)
  Not supported: 12340/13982 (88.3%)
  Warnings:      0/13982 (0.0%)
  Waived:        0/13982 (0.0%)

On DG2 (Gfx12.5) with forced lowering, Raptor Lake (Gfx12) and Ice Lake
(Gfx11):

Test run totals:
  Passed:        1662/13982 (11.9%)
  Failed:        0/13982 (0.0%)
  Not supported: 12320/13982 (88.1%)
  Warnings:      0/13982 (0.0%)
  Waived:        0/13982 (0.0%)

The difference in the number of tests run is due to
saturatingAccumulation not being set on DG2 when DPAS is used. There is
a comment in "intel/dev: Advertise integer configs with
saturatingAccumulation too" that explains how this could be added should
the need arise.

v2: Prefix type names with INTEL_CMAT_. Suggested by Lionel.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
 2023-12-29 20:28:54 -08:00
Ian Romanick 8ea032b78e intel/dev: Advertise integer configs with saturatingAccumulation too 
VUID-RuntimeSpirv-saturatingAccumulation-08983 says:

   For OpCooperativeMatrixMulAddKHR, the SaturatingAccumulation
   cooperative matrix operand must be present if and only if
   VkCooperativeMatrixPropertiesKHR::saturatingAccumulation is VK_TRUE.

As a result, we have to advertise integer configs both with and without
this flag set.

v2: Prefix type names with INTEL_CMAT_. Suggested by Lionel.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
 2023-12-29 20:28:54 -08:00
Ian Romanick f952dd510e anv: Select the SIMD mode very early when cooperative matrices are used 
The commit is a little ugly. The definition of anv_fixup_subgroup_size
is moved before the added call site. In addition, the bit starting at
the "Cooperative matrix extension requires..." comment is added.

v2: Dramatic simplification of SIMD selection. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
 2023-12-29 20:28:54 -08:00
Ian Romanick 511f91e307 anv: Lower indirect derefs again after lowering cooperative matrices 
The cooperative matrix lowering can generate a lot of indirect array
accesses, and these need to be eliminated.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
 2023-12-29 20:28:54 -08:00
Ian Romanick b741a9a851 anv: Set PIPELINE_SELECT systolic mode enable flag 
Set the flag on compute shaders when the application has enabled the
cooperative matrix feature. We might still want to enable this only when
DPAS is actually used. The current method is based on many suggestions
from Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
 2023-12-29 20:28:54 -08:00