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anv: No need to emit PIPELINE_SELECT on Xe2+

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On Xe2+, PIPELINE_SELECT is getting deprecated (Bspec 55860), as a
result we don't have to do the stalling flushes while switching between
different pipelines.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26637>
This commit is contained in:
Sagar Ghuge
2023-10-06 20:30:22 -07:00
committed by Marge Bot
parent a22297d2b1
commit 9e97ce59a8
2 changed files with 26 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/vulkan/genX_cmd_buffer.c
+12 -1
View File
@@ -6818,6 +6818,8 @@ void
genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline,
const struct anv_device *device)
{
/* Bspec 55860: Xe2+ no longer requires PIPELINE_SELECT */
#if GFX_VER < 20
anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VERx10 >= 125 ? 0x93 : GFX_VER >= 12 ? 0x13 : 0x3;
#if GFX_VER == 12
@@ -6833,6 +6835,7 @@ genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline,
device->vk.enabled_features.cooperativeMatrix;
#endif
}
#endif /* if GFX_VER < 20 */
}
static void
@@ -6844,6 +6847,14 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
if (cmd_buffer->state.current_pipeline == pipeline)
return;
#if GFX_VER >= 20
/* Since we are not stalling/flushing caches explicitly while switching
* between the pipelines, we need to apply data dependency flushes recorded
* previously on the resource.
*/
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
#else
#if GFX_VER == 9
/* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
*
@@ -6999,7 +7010,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
}
}
#endif
#endif /* else of if GFX_VER >= 20 */
cmd_buffer->state.current_pipeline = pipeline;
}
src/intel/vulkan/genX_init_state.c
+14
View File
@@ -591,19 +591,33 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero);
anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero);
anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero);
/* We no longer required to explicitly flush or invalidate caches since the
* PIPELINE_SELECT is getting deprecated on Xe2+.
*/
#if GFX_VER < 20
genx_batch_emit_pipe_control_write(&batch, device->info, _3D, NoWrite,
ANV_NULL_ADDRESS,
0,
ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS);
#endif
genX(emit_pipeline_select)(&batch, GPGPU, device);
anv_batch_emit(&batch, GENX(CFE_STATE), cfe) {
cfe.MaximumNumberofThreads =
devinfo->max_cs_threads * devinfo->subslice_total;
}
/* We no longer required to explicitly flush or invalidate caches since the
* PIPELINE_SELECT is getting deprecated on Xe2+.
*/
#if GFX_VER < 20
genx_batch_emit_pipe_control_write(&batch, device->info, _3D, NoWrite,
ANV_NULL_ADDRESS,
0,
ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS);
#endif
genX(emit_pipeline_select)(&batch, _3D, device);
#endif