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Marek Olšák 9747cf2c8f st/mesa: merge 3 unlikely blocks in _mesa_get_bufferobj_reference 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27587>
 2024-02-13 04:39:13 +00:00
Marek Olšák bfe6d389a0 mesa: remove _mesa_HashTable::InDeleteAll 
It's not necessary if we don't remove entries from the hash table,
which we don't have to do because we are going to destroy it anyway.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27586>
 2024-02-13 03:53:27 +00:00
Marek Olšák 8ca750a8b6 mesa: fold _mesa_HashDeleteAll into _mesa_DeleteHashTable 
They are always called back-to-back. This is simpler.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27586>
 2024-02-13 03:53:27 +00:00
Marek Olšák d33bffd708 mesa: re-format main/hash.h, move inlines to the end, some code to main/hash.c 
the assertions also didn't do anything

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27586>
 2024-02-13 03:53:26 +00:00
Marek Olšák cf2692fa24 mesa: clean up unnecessary _mesa_HashTable locked/unlocked wrappers 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27586>
 2024-02-13 03:53:26 +00:00
Marek Olšák 70b65fe09b mesa: remove unused _mesa_HashTable code 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27586>
 2024-02-13 03:53:26 +00:00
Marek Olšák 716e483cfb util/idalloc: make deleting invalid IDs a no-op 
This happens with piglit tests if we enable ForceGLNamesReuse
for everything.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27586>
 2024-02-13 03:53:26 +00:00
Lionel Landwerlin 5438b19104 iris: enable generated indirect draws 
This mirror the ring buffer mode we have in Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin d754ed5330 iris: add an option for not emit draw parameters 
When we start generating indirect draws, we'll generate values ourself
and point the HW vertex buffer entries to right location from the
device.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 96439b7dfb iris: factor out index buffer emission 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Kenneth Graunke 1caf42d92e iris: Implement INTEL_DEBUG=heaps 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 725817f429 iris: make URB programming available outside iris_state.c 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 84e1f8ae70 iris: make KSP helper available outside iris_state.c 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin bde1c76655 iris: make binding table shifting values available outside iris_state.c 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin f192ea630a intel/shaders: enable gfx8 support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 76c3d97c84 intel/shaders: add iris variant of indirect draws generation shader 
Iris does not use Gfx11+ SGVS extended parameters, so we have to rely
on the old Gfx9 method of providing the parameters through vertex
buffers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin b52e25d3a8 anv: rewrite internal shaders using OpenCL 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin da391650f5 ci: build a host version of mesa for cross builds 
We're about to introduce a hard dependency on OpenCL functions in Iris
& Anv to generate commands. Intel-clc has been modified to generate
serialized NIR.

A number of builders are doing cross builds, so we can't use the
intel-clc built in that cross build. Other builds like ASAN/MSAN also
complain when running the built version of intel-clc because of
uninitialized values in the packaged LLVM libraries from the
x86_64-base image.

To solve those problems we build a host version of intel-clc and use
that binary in the cross build to generate the serialized NIR.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 1e31fd5f42 meson: add option to install intel-clc 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin a26c7b0b03 intel/ds: new tracepoints for generated commands 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 472f49ef43 genxml: remove NDEBUG_UNUSED 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 41b2ed65e2 genxml: generate opencl packing headers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 2a0328ba8b genxml: enable opencl code generation 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin e6b5196079 intel-clc: print text input 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 4fd7495c69 intel/clc: add ability to output NIR 
This will be used to generate a serialized NIR of functions for
internal shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 2bae1b6b66 intel-clc: move ISA generation to its own function 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 2a1ff08376 intel/compiler: make default NIR compiler options visible 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin 012489e55c meson: add a new option to enable intel-clc without building RT shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:44 +00:00
Lionel Landwerlin c53a4711cb anv: fix incorrect flushing on shader query copy 
When doing query result copies in 3D mode, we're flushing the render
target cache, but the shader writes go through the dataport.

Fixes flakes/fails in piglit with shader query copies forced with Zink :

  $ query_copy_with_shader_threshold=0 ./bin/arb_query_buffer_object-coherency -auto -fbo

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b3b12c2c27 ("anv: enable CmdCopyQueryPoolResults to use shader for copies")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:44 +00:00
Lionel Landwerlin 2437556d83 intel/fs: rerun divergence prior to lowering non-uniform interpolate at sample 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 74a40cc4b6 ("intel/fs: move lower of non-uniform at_sample barycentric to NIR")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:44 +00:00
Lionel Landwerlin 8f5a7f57df intel/fs: indent lowering code to make it more readable 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:44 +00:00
Lionel Landwerlin c517088cf1 anv: factor out post submit queue debug code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:44 +00:00
Lionel Landwerlin 67f3fa896e intel/dev: fix missing dependency on generated packing heaers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:44 +00:00
Lepton Wu 04d26ceb0a llvmpipe: Set "+64bit" for X86_64 
Without this, on some "buggy" qemu cpu setup, LLVM could crash
if LLVM detects the wrong CPU type.

Fixes: f92cadccc6 ("llvmpipe: Always using util_get_cpu_caps to get cpu caps for llvm on x86")

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27539>
 2024-02-12 22:43:46 +00:00
Danylo Piliaiev 5dd5d4c4b5 tu: Exclude more a7xx regs from stomping 
Stomping these regs even for a short time leads to crashes.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev e4631bee61 freedreno/devices: Update magic regs for a7xx 
These regs are written by blob, for some of them blob could
write non-zero values. So executing Turnip after blob without
writing these regs could lead to nasty GPU crashes.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev eb1e71e707 freedreno,tu: Move varying interp and varying repl modes to xml 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev 78c843230c tu/a750: Consider vertex attr buff in gmem allocation 
A750 added a new optimization - placement of vertex attributes
into GMEM, so part of GMEM is carved out for it and needs to
be considered during GMEM allocations.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Mark Collins 5266815ca9 tu/a7xx: Update CCU layout logic for A7XX 
A7XX introduces some changes into the CCU such as having different
amounts of memory per CCU for depth and color and dividing up CCU
control into two registers A7XX_RB_CCU_CNTL and A7XX_RB_CCU_CNTL2
where CNTL2 no longer requires a complete flush to be updated, we
currently don't take advantage of this as any CCU updates set both
registers but it's a potential optimization we can add in the future.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev 98d6d93a82 turnip,ir3/a750: Implement inline uniforms via ldg.k 
Inline consts suffer the same issue as driver params, so they also
should be preloaded via preamble. There is special instruction to
load from global memory into consts.

Co-Authored-By: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Connor Abbott 6a744ddebc ir3: Initial support for pushing globals with ldg.k 
Add a separate pass which uses the analyze_ubo_ranges machinery to
construct ranges of readonly globals accessed in the shader and push
them to constants in the preamble, using ldg.k if possible. This is
enough to handle inline uniforms in turnip but also provides a base for
OpenCL, although the pass would need further work for that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Connor Abbott 513fa1873c ir3/a7xx: Fix load_global_ir3 with immediate offset 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Connor Abbott 45c71803f9 tu: Add more info to ldg inline uniform path 
This will let us push the ldg into the preamble.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev b87b8fdf73 tu: Use SS6_INDIRECT for VS params 
a750 has SS6_DIRECT path broken, we should either use UBO lowering
or SS6_INDIRECT path.

It is implemented as INDIRECT load even on a750+ because with UBO
lowering it would be tricky to get const offset for to use in multidraw,
also we would need to ensure the offset is not 0.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev 76e417ca59 turnip,ir3/a750: Implement consts loading via preamble 
A750 expects driver params loaded through the preamble, old path
does work but has issues when the same LOAD_STATE is used between
several draw calls (it seems that LOAD_STATE is executed only for
the first draw call).

To solve this we now lower driver params to UBOs and let NIR deal with
them.

Notes:
- VS params are loaded via old path since blob do the same and there
  are no issues observed.
- FDM is not supported at the moment.
- For now driver params data is emitted via CP_NOP because it's tricky
  to allocate space for the data. (It is emitted when we are already in
  sub_cs)

Co-Authored-By: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev 7429ca3115 tu: Use SS6_INDIRECT consts upload path for 3d blits 
3d blits used DIRECT consts upload path, which doesn't work
properly on a750+, however uploading them via SS6_INDIRECT
seem to be working.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev 30597970a5 tu/a7xx: Do not preload shaders, HW does it by default 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev ac75edb8c4 tu/a7xx: Correctly set A7XX_HLSQ_UNKNOWN_A9AE.SYSVAL_REGS_COUNT 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev bc6b847017 ir3: Add ldg.k instruction 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:13 +00:00
Danylo Piliaiev ad52f92cb8 tu: Define and set to zero all SP_*_VGPR_CONFIG regs 
SP_FS_VGPR_CONFIG was found to be correlated with blob using avgs/uvgs.
Other SP_*_VGPR_CONFIG where undefined per-stage regs and it was tested
via rddecompiler that they "fix" hangs in respective shader stage,
when such stage uses the following instructions pattern:

  avgs.s.1.tex.0
  (ss) avgs.e;
  uvgs.s.tex.0;
  uvgs.e

The exact meaning of SP_*_VGPR_CONFIG is to be investigated.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
 2024-02-12 22:05:12 +00:00