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Author SHA1 Message Date
Marek Olšák 95cbdcee83 radeonsi: add index parameter into si_atom::emit 
si_pm4_state will use si_atom, and both loops in si_emit_all_states will
be merged. This is a preparation for that because si_pm4_emit needs to know
the state index.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák cd7e20f513 radeonsi: specialize si_draw_rectangle using a C++ template 
We have only 1 variant per gfx version except gfx10+, which have 2.
The motivation is to remove instructions from si_draw_vbo.

Code size before this commit:
    si_draw_vbo<GFX11, no tess, no GS, has NGG, has pairs>: 8616 bytes
    si_draw_rectangle: 272 bytes

Code size after this commit:
    si_draw_vbo<GFX11, no tess, no GS, has NGG, has pairs>: 8534 bytes
    si_draw_rectangle<GFX11, has NGG, has pairs>: 2295 bytes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák eeb384193c radeonsi: always inline si_prefetch_shaders 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák 79e33b8b40 radeonsi: remove the draw counter with primitive restart from the HUD 
not used

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák d7f6985dd4 radeonsi: remove unused check_mem parameter from si_sampler_view_add_buffer 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák 1744a8b89c radeonsi: add padding to si_resource to fix Viewperf2020/catiav5test1 perf 
This is needed after the previous commit.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák 7d67e10b02 radeonsi: remove splitting IBs that use too much memory 
It was needed for r300, not so much for GCN/RDNA.
This reduces draw overhead.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák a59d387bc2 radeonsi: move si_emit_rasterizer_prim_state out of si_emit_all_states 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák 3a9de499b8 radeonsi: move si_emit_spi_map into si_state_shaders.cpp 
to reduce the amount of code in si_state_draw.cpp.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák e234c9fc21 radeonsi: move si_update/emit_tess_io_layout_state into si_state_shaders.cpp 
to reduce the amount of code in si_state_draw.cpp.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák 9999660386 radeonsi: remove si_compute.h, move the contents into si_pipe.h 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák a10c46d8a6 radeonsi: update obsolete comments about compiler queues 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák cb7dcdcea0 radeonsi: handle draw user SGPRs as tracked registers 
instead of this custom code doing the same thing. This tracks changes to LS,
ES, and VS user SGPRs separately, so that we can skip more redundant register
changes when enabling/disabling GS and tess. The perf impact should be neutral.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:06 +00:00
Marek Olšák 3f34bd5f3f radeonsi: cosmetic changes to radeon_opt_* macros 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:05 +00:00
Marek Olšák a5b3165774 radeonsi: restructure the loop for non-indexed multi draws 
Have one loop for increment_draw_id and another loop without it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:05 +00:00
Marek Olšák c30aed0002 radeonsi: turn sh_base[PIPE_SHADER_VERTEX] into a constant in emit_draw_packets 
HAS_TESS will also be used in the next commit

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>
 2023-08-17 15:34:05 +00:00
Jason Ekstrand f34f740b64 spirv: Re-emit constants at their uses 
Right now, spirv_to_nir places all constants at the top of the function
and has a hash table to de-duplicate them.  This change drops the hash
table and starts re-emitting constants more-or-less at their uses.  This
is more consistent with what we do in GLSL -> NIR translation.  It is,
however, a change to SPIR-V -> NIR translation which will likely affect
other optimizations in unexpected ways so it should be evaluated
separately.

This gives some good saves for spills/fills for Intel, without causing
any significant regressions on RADV, because it is using the
nir_opt_reuse_constants() pass.  In the long run that should be superseded
by some form of GCM.

```
Intel TGL results for Intel fossils:

Totals:
Instrs: 183287977 -> 183269431 (-0.01%); split: -0.07%, +0.06%
Cycles: 18224600804 -> 18223114114 (-0.01%); split: -0.16%, +0.15%
Spill count: 111031 -> 108377 (-2.39%); split: -2.45%, +0.06%
Fill count: 221781 -> 216479 (-2.39%); split: -2.39%, +0.00%
Scratch Memory Size: 4355072 -> 4180992 (-4.00%); split: -5.31%, +1.32%

Totals from 43684 (6.54% of 667704) affected shaders:
Instrs: 38289482 -> 38270936 (-0.05%); split: -0.33%, +0.28%
Cycles: 7166415272 -> 7164928582 (-0.02%); split: -0.40%, +0.38%
Spill count: 93747 -> 91093 (-2.83%); split: -2.90%, +0.07%
Fill count: 190943 -> 185641 (-2.78%); split: -2.78%, +0.00%
Scratch Memory Size: 3127296 -> 2953216 (-5.57%); split: -7.40%, +1.83%
```

```
RADV GFX1100 results for radv fossils:

Totals:
Instrs: 71623708 -> 71624667 (+0.00%); split: -0.00%, +0.01%
CodeSize: 369324312 -> 369334744 (+0.00%); split: -0.00%, +0.01%
SpillSGPRs: 13586 -> 13582 (-0.03%)
SpillVGPRs: 911 -> 910 (-0.11%); split: -0.55%, +0.44%
Latency: 632887831 -> 632880378 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 81674859 -> 81676684 (+0.00%); split: -0.00%, +0.01%
VClause: 1273752 -> 1273727 (-0.00%); split: -0.00%, +0.00%
SClause: 2409593 -> 2409078 (-0.02%); split: -0.02%, +0.00%
Copies: 4063579 -> 4064425 (+0.02%); split: -0.05%, +0.07%
Branches: 1196723 -> 1196720 (-0.00%); split: -0.00%, +0.00%

Totals from 16244 (12.17% of 133461) affected shaders:
Instrs: 31116807 -> 31117766 (+0.00%); split: -0.01%, +0.01%
CodeSize: 160316656 -> 160327088 (+0.01%); split: -0.01%, +0.01%
SpillSGPRs: 12270 -> 12266 (-0.03%)
SpillVGPRs: 835 -> 834 (-0.12%); split: -0.60%, +0.48%
Latency: 344388549 -> 344381096 (-0.00%); split: -0.01%, +0.00%
InvThroughput: 43043761 -> 43045586 (+0.00%); split: -0.01%, +0.01%
VClause: 433221 -> 433196 (-0.01%); split: -0.01%, +0.00%
SClause: 900825 -> 900310 (-0.06%); split: -0.06%, +0.00%
Copies: 1989000 -> 1989846 (+0.04%); split: -0.11%, +0.15%
Branches: 676625 -> 676622 (-0.00%); split: -0.00%, +0.00%
```

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>
 2023-08-17 14:58:02 +00:00
Caio Oliveira 39e24082fc radv: Use nir_opt_reuse_constants() 
Right now, this won't change much the shaders since most of the NIR constants
are reused in the NIR generated by SPIR-V, but will make radv resilient to
when that behavior change.

```
RADV GFX1100 results for radv fossils:

Totals:
Instrs: 71623585 -> 71623708 (+0.00%); split: -0.00%, +0.00%
CodeSize: 369326156 -> 369324312 (-0.00%); split: -0.00%, +0.00%
SpillSGPRs: 13576 -> 13586 (+0.07%)
Latency: 632889681 -> 632887831 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 81674616 -> 81674859 (+0.00%); split: -0.00%, +0.00%
SClause: 2409601 -> 2409593 (-0.00%); split: -0.00%, +0.00%
Copies: 4063438 -> 4063579 (+0.00%); split: -0.00%, +0.01%
Branches: 1196703 -> 1196723 (+0.00%)
PreSGPRs: 4242897 -> 4243061 (+0.00%); split: -0.00%, +0.00%
PreVGPRs: 3926739 -> 3926742 (+0.00%)

Totals from 217 (0.16% of 133461) affected shaders:
Instrs: 353567 -> 353690 (+0.03%); split: -0.04%, +0.07%
CodeSize: 1790200 -> 1788356 (-0.10%); split: -0.15%, +0.04%
SpillSGPRs: 8 -> 18 (+125.00%)
Latency: 5152817 -> 5150967 (-0.04%); split: -0.05%, +0.01%
InvThroughput: 664273 -> 664516 (+0.04%); split: -0.03%, +0.06%
SClause: 10164 -> 10156 (-0.08%); split: -0.10%, +0.02%
Copies: 24225 -> 24366 (+0.58%); split: -0.32%, +0.90%
Branches: 7116 -> 7136 (+0.28%)
PreSGPRs: 13351 -> 13515 (+1.23%); split: -0.16%, +1.39%
PreVGPRs: 11583 -> 11586 (+0.03%)
```

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>
 2023-08-17 14:58:02 +00:00
Caio Oliveira 74746ac03a nir: Add nir_opt_reuse_constants() 
Currently SPIR-V does pull all the NIR constants it creates into the
first block, but we plan to change that behavior to let those constants
be defined as they are used.

This pass was written to provide a fallback to the old behavior, it will
be used for radv to avoid regressions when performing the SPIR-V change.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>
 2023-08-17 14:58:02 +00:00
Gert Wollny d80392a6df r600: use correct cso pointer for fetch shader 
Fixes: 76725452 (gallium: move vertex stride to CSO)

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9567

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24728>
 2023-08-17 14:27:51 +00:00
David Heidelberg 9d442b459a ci/freedreno: handle disabling farm properly for each FD/Collabora farm 
To acknowledge for disable freedreno or collabora farm, split definitions into:
 - google-* (a306, a530, a630)
 - collabora-* (a618, a660)

This let us control when jobs will run. This rules gets also used in zink.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>
 2023-08-17 13:25:46 +00:00
David Heidelberg e6928735e6 ci/freedreno: switch references, the farm-rules takes care about this 
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>
 2023-08-17 13:25:46 +00:00
David Heidelberg e62527c2d0 ci/freedreno: the tag belongs to the apq8016 only 
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>
 2023-08-17 13:25:46 +00:00
David Heidelberg bcf5288351 ci/zink: drop a630, which we currently have very low amount available 
It's disabled anyway.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>
 2023-08-17 13:25:46 +00:00
David Heidelberg 3a4bdf26e6 ci: remove LAVA prefix from variables which can be used also elsewhere 
At least these two can be easily used in bare-metal or Labgrid setups.

Currently I already have MR for implementing these for Labgrid.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24665>
 2023-08-17 13:25:46 +00:00
Mike Blumenkrantz 8f3499bafc Revert "vk/wsi/x11: handle geometry updating more asynchronously" 
This reverts commit 36d5b58317.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24742>
 2023-08-17 12:52:35 +00:00
Karol Herbst cc2f59d840 rusticl/kernel: optimize nir between lowering io and explicit types 
This is required to get rid of unneeded memory operations, like direct
scratch stores/loads to the same location.

Fixes: 66c6061491 ("rusticl/kernel: get rid of initial function_temp type lowering")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24734>
 2023-08-17 12:34:26 +00:00
Karol Herbst 91029b7e87 nouveau: take glsl_type ref unconditionally 
Calling into tgsi_to_nir requires it, which we are running into with vdpau
and potential other state-trackers still handing us TGSIs over.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9481
Fixes: 5889c13fcd ("nv50,nvc0: Use ttn for tgsi shaders by default")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24740>
 2023-08-17 12:12:56 +00:00
Mike Blumenkrantz 0fb9064231 vk/graphics: fix CWE handling with DS3 
VkPipelineColorBlendStateCreateInfo::attachmentCount cannot be used to
generate the CWE mask since it cannot be read if enough dynamic state is in use

instead just pass the max mask and let drivers figure it out

cc: mesa-stable

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24673>
 2023-08-17 11:01:36 +00:00
Christian Gmeiner e13bdbbd5b etnaviv: switch to float_to_ubyte(..) 
The blob generates following values for e.g. this call.
  glBlendColor(0.002000f, 0.018000f, 0.030000f, 1.0)

  0xff010508, /*   [01424] PE.ALPHA_BLEND_COLOR := B=0x8,G=0x5,R=0x1,A=0xff */

etnaviv's etna_cfloat_to_uint8(..) creates different values.

  0.002000: 0x0
  0.018000: 0x4
  0.030000: 0x7

The same applies for the alpha reference value.

Lets drop this hand-rolled conversion helper to get the same values as
blob.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24727>
 2023-08-17 09:42:20 +00:00
Tapani Pälli 98eecece9b anv: remove assert, size is asserted in the runtime 
Otherwise gets hit on Android CTS tests.

Reported-by: Chris Spencer <spencercw@gmail.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24722>
 2023-08-17 08:36:15 +00:00
Tapani Pälli 2cbe85e6a9 vulkan/runtime: change assert to match specification needs 
Otherwise gets hit on Android CTS tests.

Reported-by: Chris Spencer <spencercw@gmail.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24722>
 2023-08-17 08:36:15 +00:00
Marek Olšák 20d6bb2769 glthread: sync for VDPAU sync functions 
They should sync according to the spec.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24528>
 2023-08-17 04:53:37 +00:00
Emma Anholt 5a8672952a freedreno/a3-5xx: Don't try to emit ISAM for SSBO loads. 
We don't emit tex descriptors for the SSBOs, so if we took this path we'd
fault.

Fixes: 75eb0d2891 ("freedreno/ir3: Allow isam for non-bindless ssbo loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24682>
 2023-08-17 01:18:19 +00:00
Emma Anholt 408199236f ci/freedreno: Skip some tests on a5xx that destabilize other tests. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24682>
 2023-08-17 01:18:19 +00:00
Konstantin Seurer 3aa3eb8ddd nir/opt_large_constants: Handle small float arrays 
Handles small arrays of integer, positive floats.

RADV fossils:

Totals from 65 (0.05% of 131205) affected shaders:
Instrs: 30001 -> 29936 (-0.22%); split: -0.39%, +0.18%
CodeSize: 165676 -> 164996 (-0.41%); split: -0.53%, +0.12%
Latency: 126873 -> 127178 (+0.24%); split: -0.29%, +0.53%
InvThroughput: 26640 -> 26895 (+0.96%); split: -0.48%, +1.44%
VClause: 425 -> 371 (-12.71%)
SClause: 982 -> 981 (-0.10%); split: -0.92%, +0.81%
Copies: 2072 -> 1939 (-6.42%); split: -6.52%, +0.10%
PreVGPRs: 1553 -> 1537 (-1.03%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Faith Ekstrand e38522608f nir/opt_large_constants: Add Small constant handling 
Adds handling for constant arrays that can be lowered to
'(imm >> bit_index) & bit_mask' instead of constant loads.

RADV fossils:

Totals from 70 (0.05% of 131205) affected shaders:
Instrs: 31441 -> 31260 (-0.58%); split: -0.59%, +0.02%
CodeSize: 172104 -> 170568 (-0.89%)
VGPRs: 2608 -> 2616 (+0.31%)
Latency: 296687 -> 280859 (-5.33%); split: -5.34%, +0.00%
InvThroughput: 65491 -> 65696 (+0.31%); split: -0.11%, +0.42%
VClause: 671 -> 646 (-3.73%)
SClause: 1014 -> 964 (-4.93%)
Copies: 1742 -> 1564 (-10.22%); split: -10.51%, +0.29%
PreSGPRs: 2039 -> 2036 (-0.15%)
PreVGPRs: 2014 -> 2017 (+0.15%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Faith Ekstrand 8ec0fdf017 nir/large_constants: Add read/write_const_values helpers 
The write helper is just pulling code we already have out into a helper
and flipping the order of the loop and the switch.  The read helper will
be useful in the next commit where we add small constant support.  This
keeps the two helpers right next to each other in the file where they're
easy to compare and we can ensure that they stay in sync.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Faith Ekstrand 7456ee0523 nir/large_constants: Use nir_component_mask_t 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Mohamed Ahmed 783d59eec1 nil: Add support for G8B8_G8R8_UNORM and B8G8_R8G8_UNORM 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>
 2023-08-16 22:36:27 +00:00
Mohamed Ahmed c7f109352d nvk: Enable MIDPOINT_CHROMA_SAMPLES_BIT for multi-planar formats only 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>
 2023-08-16 22:36:27 +00:00
Mohamed Ahmed b9801a3c08 nvk: Enable SEPARATE_RECONSTRUCTION_FILTER_BIT for multi-planar formats only 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>
 2023-08-16 22:36:27 +00:00
Faith Ekstrand 4e2830c9ef nir: Clean up nir_op_is_vec() and its callers 
The nir_op_is_vec() helper I added in 842338e2f0 ("nir: Add a
nir_op_is_vec helper") treats nir_op_mov as a vec even though the
semanitcs of the two are different.  In retrospect, this was a mistake
as the previous three fixup commits show.  This commit splits the helper
into two: nir_op_is_vec() and nir_op_is_vec_or_mov() and uses the
appropriate helper at each call site.  Hopefully, this rename will
encurage any future users of these helpers to think about nir_op_mov as
separate from nir_op_vecN and we can avoid these bugs.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand 408929289a nir: Don't handle nir_op_mov in get_undef_mask in opt_undef 
It's unnecessary because earlier parts of the pass will ensure that a
mov of undef is turned into an undef.  It's also wrong because
nir_op_mov has different semantics from nir_op_vecN when it comes to how
sources map to destination components.

Fixes: 5f26c21e62 ("nir: Expand opt_undef to handle undef channels in a store intrinsic")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand f9a17c6fef nir: Handle nir_op_mov properly in opt_shrink_vectors 
If the opcode is a mov, it falls into the nir_alu_src_is_trivial_ssa
case, not the vec case.

Fixes: 94eff7ccd8 ("nir: shrink phi nodes in nir_opt_shrink_vectors")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand 9bcc9597a5 nir: Fix nir_op_mov handling in nir_collect_src_uniforms 
For mov we need to follow the swizzle for the destination component, not
grab swizzle[0] for some random source.

Fixes: a406fff78a ("nir/inline_uniforms: support vector uniform")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand 87004fa701 nir: Rework nir_scalar_chase_movs a bit 
The cases in the if are the same as the cases we're using for the early
break.  Just check the things and break if it's not a handleable case.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Rhys Perry cf796aa885 radv: vectorize scratch access 
fossil-db (gfx1100):
Totals from 20 (0.01% of 133461) affected shaders:
Instrs: 49421 -> 49134 (-0.58%)
CodeSize: 251668 -> 249604 (-0.82%); split: -0.83%, +0.01%
Latency: 178126 -> 178412 (+0.16%); split: -0.16%, +0.32%
InvThroughput: 23565 -> 23646 (+0.34%); split: -0.05%, +0.39%
VClause: 957 -> 943 (-1.46%)
Copies: 5770 -> 5801 (+0.54%); split: -0.36%, +0.90%
PreVGPRs: 1368 -> 1359 (-0.66%)

Regressions seem to be a couple of cases of bad RA luck.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry 81641b0155 radv: vectorize RT stack access 
fossil-db (gfx1100):
Totals from 10 (0.01% of 133461) affected shaders:
MaxWaves: 176 -> 174 (-1.14%)
Instrs: 39260 -> 38710 (-1.40%)
CodeSize: 202272 -> 197288 (-2.46%)
VGPRs: 888 -> 900 (+1.35%)
Latency: 82306 -> 81762 (-0.66%); split: -0.68%, +0.02%
InvThroughput: 11182 -> 11158 (-0.21%); split: -0.52%, +0.30%
VClause: 721 -> 700 (-2.91%)
SClause: 1147 -> 1148 (+0.09%); split: -0.17%, +0.26%
Copies: 3625 -> 3891 (+7.34%)
PreVGPRs: 819 -> 845 (+3.17%); split: -0.37%, +3.54%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry 6f315e6049 nir/opt_load_store_vectorize: support scratch access 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00