radeonsi: add index parameter into si_atom::emit

si_pm4_state will use si_atom, and both loops in si_emit_all_states will
be merged. This is a preparation for that because si_pm4_emit needs to know
the state index.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24732>

src/gallium/drivers/radeonsi/gfx11_query.c

@@ -12,7 +12,7 @@
 
 #include <stddef.h>
 
-static void emit_shader_query(struct si_context *sctx)
+static void emit_shader_query(struct si_context *sctx, unsigned index)
 {
    assert(!list_is_empty(&sctx->shader_query_buffers));
 

src/gallium/drivers/radeonsi/si_compute.c

@@ -1027,7 +1027,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
       sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
 
    if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
-      sctx->atoms.s.render_cond.emit(sctx);
+      sctx->atoms.s.render_cond.emit(sctx, -1);
       si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
    }
 

src/gallium/drivers/radeonsi/si_descriptors.c

@@ -2221,7 +2221,7 @@ static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_de
    radeon_end();
 }
 
-void si_emit_graphics_shader_pointers(struct si_context *sctx)
+void si_emit_graphics_shader_pointers(struct si_context *sctx, unsigned index)
 {
    uint32_t *sh_base = sctx->shader_pointers.sh_base;
 

src/gallium/drivers/radeonsi/si_pipe.h

@@ -1323,7 +1323,7 @@ struct si_context {
    /* When b.draw_vbo is a wrapper, real_draw_vbo is the real draw_vbo function */
    pipe_draw_vbo_func real_draw_vbo;
    pipe_draw_vertex_state_func real_draw_vertex_state;
-   void (*emit_spi_map[33])(struct si_context *sctx);
+   void (*emit_spi_map[33])(struct si_context *sctx, unsigned index);
 
    /* SQTT */
    struct ac_sqtt *sqtt;

src/gallium/drivers/radeonsi/si_pm4.c

@@ -337,7 +337,7 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
    radeon_end();
 
    if (state->atom.emit)
-      state->atom.emit(sctx);
+      state->atom.emit(sctx, -1);
 }
 
 void si_pm4_reset_emitted(struct si_context *sctx)

src/gallium/drivers/radeonsi/si_pm4.h

@@ -22,7 +22,8 @@ struct si_context;
  * command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
  */
 struct si_atom {
-   void (*emit)(struct si_context *ctx);
+   /* The index is only used by si_pm4_emit_state. Non-pm4 atoms don't use it. */
+   void (*emit)(struct si_context *ctx, unsigned index);
 };
 
 struct si_pm4_state {

src/gallium/drivers/radeonsi/si_query.c

@@ -1027,7 +1027,7 @@ static void emit_set_predicate(struct si_context *ctx, struct si_resource *buf,
    radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_READ | RADEON_PRIO_QUERY);
 }
 
-static void si_emit_query_predication(struct si_context *ctx)
+static void si_emit_query_predication(struct si_context *ctx, unsigned index)
 {
    uint32_t op;
    bool flag_wait, invert;

src/gallium/drivers/radeonsi/si_state.c

@@ -50,7 +50,7 @@ static unsigned si_pack_float_12p4(float x)
  * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
  * if there is not enough PS outputs.
  */
-static void si_emit_cb_render_state(struct si_context *sctx)
+static void si_emit_cb_render_state(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    struct si_state_blend *blend = sctx->queued.named.blend;
@@ -806,7 +806,7 @@ static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend
    si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
 }
 
-static void si_emit_blend_color(struct si_context *sctx)
+static void si_emit_blend_color(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
 
@@ -840,7 +840,7 @@ static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_s
    si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
 }
 
-static void si_emit_clip_state(struct si_context *sctx)
+static void si_emit_clip_state(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
 
@@ -850,7 +850,7 @@ static void si_emit_clip_state(struct si_context *sctx)
    radeon_end();
 }
 
-static void si_emit_clip_regs(struct si_context *sctx)
+static void si_emit_clip_regs(struct si_context *sctx, unsigned index)
 {
    struct si_shader *vs = si_get_vs(sctx)->current;
    struct si_shader_selector *vs_sel = vs->selector;
@@ -1253,7 +1253,7 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state)
 /*
  * inferred state between dsa and stencil ref
  */
-static void si_emit_stencil_ref(struct si_context *sctx)
+static void si_emit_stencil_ref(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
@@ -1529,7 +1529,7 @@ void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
    sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
 }
 
-static void si_emit_db_render_state(struct si_context *sctx)
+static void si_emit_db_render_state(struct si_context *sctx, unsigned index)
 {
    unsigned db_shader_control, db_render_control, db_count_control, vrs_override_cntl = 0;
 
@@ -3099,7 +3099,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
    }
 }
 
-static void si_emit_framebuffer_state(struct si_context *sctx)
+static void si_emit_framebuffer_state(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
@@ -3617,7 +3617,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
    return true;
 }
 
-static void si_emit_msaa_config(struct si_context *sctx)
+static void si_emit_msaa_config(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
@@ -4834,7 +4834,7 @@ static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
    si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
 }
 
-static void si_emit_sample_mask(struct si_context *sctx)
+static void si_emit_sample_mask(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    unsigned mask = sctx->sample_mask;

src/gallium/drivers/radeonsi/si_state.h

@@ -556,7 +556,7 @@ void si_add_all_descriptors_to_bo_list(struct si_context *sctx);
 void si_update_all_texture_descriptors(struct si_context *sctx);
 void si_shader_change_notify(struct si_context *sctx);
 void si_update_needs_color_decompress_masks(struct si_context *sctx);
-void si_emit_graphics_shader_pointers(struct si_context *sctx);
+void si_emit_graphics_shader_pointers(struct si_context *sctx, unsigned index);
 void si_emit_compute_shader_pointers(struct si_context *sctx);
 void si_set_internal_const_buffer(struct si_context *sctx, uint slot,
                                   const struct pipe_constant_buffer *input);
@@ -598,7 +598,7 @@ struct si_fast_udiv_info32 {
 struct si_fast_udiv_info32 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits);
 
 /* si_state_binning.c */
-void si_emit_dpbb_state(struct si_context *sctx);
+void si_emit_dpbb_state(struct si_context *sctx, unsigned index);
 
 /* si_state_shaders.cpp */
 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,

src/gallium/drivers/radeonsi/si_state_binning.c

@@ -423,7 +423,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
    radeon_end_update_context_roll(sctx);
 }
 
-void si_emit_dpbb_state(struct si_context *sctx)
+void si_emit_dpbb_state(struct si_context *sctx, unsigned index)
 {
    struct si_screen *sscreen = sctx->screen;
    struct si_state_blend *blend = sctx->queued.named.blend;

src/gallium/drivers/radeonsi/si_state_draw.cpp

@@ -1942,7 +1942,8 @@ static void si_emit_all_states(struct si_context *sctx, unsigned skip_atom_mask)
    unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
    if (mask) {
       do {
-         sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
+         unsigned i = u_bit_scan(&mask);
+         sctx->atoms.array[i].emit(sctx, i);
       } while (mask);
 
       sctx->dirty_atoms &= skip_atom_mask;
@@ -2278,14 +2279,14 @@ static void si_draw(struct pipe_context *ctx,
     * do it now.
     */
    if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
-      sctx->atoms.s.render_cond.emit(sctx);
+      sctx->atoms.s.render_cond.emit(sctx, -1);
       sctx->dirty_atoms &= ~si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
    }
 
    /* This needs to be done after cache flushes because ACQUIRE_MEM rolls the context. */
    if (GFX_VERSION == GFX9 && gfx9_scissor_bug &&
        (sctx->context_roll || si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
-      sctx->atoms.s.scissors.emit(sctx);
+      sctx->atoms.s.scissors.emit(sctx, -1);
       sctx->dirty_atoms &= ~si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
    }
    assert(sctx->dirty_atoms == 0);

src/gallium/drivers/radeonsi/si_state_msaa.c

@@ -163,7 +163,7 @@ static void si_emit_max_16_sample_locs(struct radeon_cmdbuf *cs, uint64_t centro
    radeon_end();
 }
 
-static void si_emit_sample_locations(struct si_context *sctx)
+static void si_emit_sample_locations(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;

src/gallium/drivers/radeonsi/si_state_shaders.cpp

@@ -607,8 +607,9 @@ static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_sh
    }
 }
 
-static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader,
-                                                    void (*emit_func)(struct si_context *ctx))
+static struct si_pm4_state *
+si_get_shader_pm4_state(struct si_shader *shader,
+                        void (*emit_func)(struct si_context *ctx, unsigned index))
 {
    si_pm4_clear_state(&shader->pm4, shader->selector->screen, false);
    shader->pm4.is_shader = true;
@@ -753,7 +754,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
    si_pm4_finalize(pm4);
 }
 
-static void si_emit_shader_es(struct si_context *sctx)
+static void si_emit_shader_es(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.es;
 
@@ -913,7 +914,7 @@ void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *
    assert(out->max_prims_per_subgroup <= max_out_prims);
 }
 
-static void si_emit_shader_gs(struct si_context *sctx)
+static void si_emit_shader_gs(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.gs;
 
@@ -1208,14 +1209,14 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader
    radeon_end();
 }
 
-static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
+static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.gs;
 
    gfx10_emit_shader_ngg_tail(sctx, shader);
 }
 
-static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
+static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.gs;
 
@@ -1227,7 +1228,7 @@ static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
    gfx10_emit_shader_ngg_tail(sctx, shader);
 }
 
-static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
+static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.gs;
 
@@ -1239,7 +1240,7 @@ static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
    gfx10_emit_shader_ngg_tail(sctx, shader);
 }
 
-static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
+static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.gs;
 
@@ -1521,7 +1522,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
    si_pm4_finalize(pm4);
 }
 
-static void si_emit_shader_vs(struct si_context *sctx)
+static void si_emit_shader_vs(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.vs;
 
@@ -1746,7 +1747,7 @@ static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
    return value;
 }
 
-static void si_emit_shader_ps(struct si_context *sctx)
+static void si_emit_shader_ps(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.ps;
 
@@ -4163,7 +4164,7 @@ void si_init_tess_factor_ring(struct si_context *sctx)
    si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 }
 
-static void si_emit_vgt_pipeline_state(struct si_context *sctx)
+static void si_emit_vgt_pipeline_state(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
 
@@ -4173,7 +4174,7 @@ static void si_emit_vgt_pipeline_state(struct si_context *sctx)
    radeon_end_update_context_roll(sctx);
 }
 
-static void si_emit_scratch_state(struct si_context *sctx)
+static void si_emit_scratch_state(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
 
@@ -4511,7 +4512,7 @@ void si_update_tess_io_layout_state(struct si_context *sctx)
    si_mark_atom_dirty(sctx, &sctx->atoms.s.tess_io_layout);
 }
 
-static void si_emit_tess_io_layout_state(struct si_context *sctx)
+static void si_emit_tess_io_layout_state(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    radeon_begin(cs);
@@ -4603,7 +4604,7 @@ void si_init_screen_live_shader_cache(struct si_screen *sscreen)
 }
 
 template<int NUM_INTERP>
-static void si_emit_spi_map(struct si_context *sctx)
+static void si_emit_spi_map(struct si_context *sctx, unsigned index)
 {
    struct si_shader *ps = sctx->shader.ps.current;
    struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;

src/gallium/drivers/radeonsi/si_state_streamout.c

@@ -232,7 +232,7 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
    radeon_end();
 }
 
-static void si_emit_streamout_begin(struct si_context *sctx)
+static void si_emit_streamout_begin(struct si_context *sctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
    struct si_streamout_target **t = sctx->streamout.targets;
@@ -360,7 +360,7 @@ void si_emit_streamout_end(struct si_context *sctx)
  * are no buffers bound.
  */
 
-static void si_emit_streamout_enable(struct si_context *sctx)
+static void si_emit_streamout_enable(struct si_context *sctx, unsigned index)
 {
    assert(sctx->gfx_level < GFX11);
 

src/gallium/drivers/radeonsi/si_state_viewport.c

@@ -68,7 +68,7 @@ static void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small
    *out = info;
 }
 
-static void si_emit_cull_state(struct si_context *sctx)
+static void si_emit_cull_state(struct si_context *sctx, unsigned index)
 {
    assert(sctx->screen->use_ngg_culling);
 
@@ -248,7 +248,7 @@ static void si_emit_one_scissor(struct si_context *ctx, struct radeon_cmdbuf *cs
 
 #define MAX_PA_SU_HARDWARE_SCREEN_OFFSET 8176
 
-static void si_emit_guardband(struct si_context *ctx)
+static void si_emit_guardband(struct si_context *ctx, unsigned index)
 {
    const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
    struct si_signed_scissor vp_as_scissor;
@@ -385,7 +385,7 @@ static void si_emit_guardband(struct si_context *ctx)
    radeon_end_update_context_roll(ctx);
 }
 
-static void si_emit_scissors(struct si_context *ctx)
+static void si_emit_scissors(struct si_context *ctx, unsigned index)
 {
    struct radeon_cmdbuf *cs = &ctx->gfx_cs;
    struct pipe_scissor_state *states = ctx->scissors;
@@ -565,7 +565,7 @@ static void si_emit_depth_ranges(struct si_context *ctx)
    radeon_end();
 }
 
-static void si_emit_viewport_states(struct si_context *ctx)
+static void si_emit_viewport_states(struct si_context *ctx, unsigned index)
 {
    si_emit_viewports(ctx);
    si_emit_depth_ranges(ctx);
@@ -616,7 +616,7 @@ void si_update_vs_viewport_state(struct si_context *ctx)
    }
 }
 
-static void si_emit_window_rectangles(struct si_context *sctx)
+static void si_emit_window_rectangles(struct si_context *sctx, unsigned index)
 {
    /* There are four clipping rectangles. Their corner coordinates are inclusive.
     * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending