AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
168,503 Commits 1 Branch 0 Tags
94de8767aa818ecdbe1fc13380f9cac42622f919
Commit Graph

168503 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
SoroushIMG 4f8ba2b9aa zink: fix sparse residency query and minLOD feature checks 
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21013>
 2023-02-03 20:05:23 +00:00
Yiwei Zhang 86c6484fba venus: lazily query and cache gralloc front rendering usage 
When skiavk is the default system ui renderer, venus icd gets preloaded
into Zygote. However, Zygote access to render node is normally denied by
selinux except for legacy bootanimation purpose. This change fixes venus
icd loading to avoid invoking cros gralloc driver loading by moving the
perform op outside, so that we still get the memory footprint win.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21107>
 2023-02-03 19:33:18 +00:00
Emma Anholt de5b67ef2c ci/llvmpipe: Drop skip of InteractionFunctionCalls2. 
This one is down to <5 seconds here these days.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>
 2023-02-03 19:01:59 +00:00
Emma Anholt 2eb07304e3 ci/swrast: Drop skips for tests whose perf had been fixed. 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>
 2023-02-03 19:01:59 +00:00
Emma Anholt 907b0a01b7 gallivm: Do the same codegen improvement for constant-index array loads. 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>
 2023-02-03 19:01:59 +00:00
Emma Anholt cf47154300 gallivm: Fix codegen performance for constant-index register array stores. 
Instead of generating num_components*simdwidth scattered stores, if
there's no indirect then we can just look up the pointer to the
base_offset and do a simd store there.

dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i64vec4 goes
from 30s to ~2s.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>
 2023-02-03 19:01:59 +00:00
Emma Anholt 833a74351c gallivm: Fix the type of array nir_registers. 
This now matches how they get dereffed by get_soa_array_offsets() -- each
array element has num_components vecs inside of it, rather than each
components has an array in it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>
 2023-02-03 19:01:59 +00:00
Emma Anholt a5d360550e gallivm: Enable GALLIVM_DEBUG (mostly) on non-DEBUG builds. 
This is what let me do the performance work in my recent gallivm MRs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21086>
 2023-02-03 18:21:49 +00:00
Emma Anholt 947c60fa2f llvmpipe: Enable LP_DEBUG on normal builds. 
I don't typically include DEBUG because it sometimes has expensive debug
code, but these options are not that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21086>
 2023-02-03 18:21:49 +00:00
Dylan Baker fd9b50aa1c meson: combine checks for linker --gc-sections support 
We first do an incomplete check for whether the linker supports
--gc-sections, then potentially add C and C++ arguments assuming that it
works, then later do a complete check to see if it actually works and
use --gc-sections. This means we can end up putting functions and data
in separate sections when we can't gc them.

Combine the checks, do less work, and be more accurate.

fixes: f51ce21e4e
       ("meson: Drop adding -Wl,--gc-sections to project c/cpp arguments.")

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21083>
 2023-02-03 17:48:58 +00:00
Alyssa Rosenzweig 7f98a9ba2b panfrost: Implement GL_EXT_render_snorm on Bifrost+ 
It turns out it's really easy.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20684>
 2023-02-03 17:21:34 +00:00
Emma Anholt b6bd904019 ci/lvp: Drop the subgroupbroadcast skips. 
These have the same runtime as the others in the group, and with these
optimizations they no longer time out.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
 2023-02-03 08:51:42 -08:00
Emma Anholt 70be21e7c6 gallivm: Use first active invocation in some image/ssbo accesses. 
These should be looking at that rather than blindly using invocation 0
(which may be junk when in control flow).

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
 2023-02-03 08:51:40 -08:00
Emma Anholt 8c2493d041 gallivm: Use cttz instead of a loop for first_active_invocation(). 
This should be way faster to compile by not spamming so many loops at
LLVM, and faster to execute if LLVM didn't figure out what that loop
meant.

It looks vector reduce ops aren't really a thing, just a convenience in
the IR.  We should be able to do better by counting zeroes in the
exec_mask != 0 result.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
 2023-02-03 08:51:37 -08:00
Emma Anholt c11fa55f6d gallivm: Return 0 first_active_invocation when we know that up front. 
46 -> 30 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4 by
not spamming LLVM with so many loops.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
 2023-02-03 08:51:35 -08:00
Emma Anholt dc7c518abe gallivm: Refactor out a shared "get the first active invocation" loop. 
Dynamic texture indices had a similar "find an active channel" loop,
though it happened to use the last active channel rather than the first.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
 2023-02-03 08:51:32 -08:00
Emma Anholt 0b0246706e gallivm: Optimize emit_read_invocation's first-invocation loop. 
We don't need to deref invoc inside -- invoc is uniform in active
channels, so we can find our first active invocation in the loop, and then
dereference invocation once outside.

50 -> 46 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
 2023-02-03 08:51:12 -08:00
Alyssa Rosenzweig d73f72120a asahi: Lower texcoords late 
This uses the new pass to lower tex coordinates late, which gets us one step
closer to preprocessing NIR at CSO create time instead of variant create time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
 2023-02-03 15:03:06 +00:00
Alyssa Rosenzweig 6908a0dece asahi: Run nir_lower_fragcolor during preprocessing 
This pass needs to run early (because it depends on early I/O), but it doesn't
actually need the shader key. Why not? If we overestimate the number of render
targets, extra store_output intrinsics will be generated, but they will be
deleted by AGX tilebuffer lowering later.

Note we'll probably want something smarter than this for fragment epilogues in
the future to avoid piles of unnecessary moves.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
 2023-02-03 15:03:06 +00:00
Alyssa Rosenzweig 071ac59960 nir: Add a late texcoord replacement pass 
Add a second NIR pass for lowering point/texture coordinate replacement (i.e.
point sprites). Why a second one? The current pass works on derefs/variables,
which is good for drivers that don't lower I/O at all (like Zink, where the pass
originates). However, it is problematic for hardware drivers: the inputs to this
pass depend on the shader key, so we want to run the pass as late as possible to
minimize the cost of building/compiling the associated shader variants. In
particular, we need to be able to lower point sprites after lowering I/O if we
would like to lower I/O when preprocessing NIR.

The logic for early lowering and late lowering is considerably different (the
late lowering is a lot simpler), so I've split this out into a second pass
rather than trying to weld them together into one.

This pass will be used on Asahi, which currently uses the early pass. It may be
useful for other drivers as well. (Actually, it's been shipping on Asahi for a
little while now, just hasn't been sent upstream yet.)

Tested with Neverball.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Asahi Lina <lina@asahilina.net>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
 2023-02-03 15:03:06 +00:00
Konstantin Seurer 4397c166c0 radv: Work around shader_call_data variables in raygen shaders 
Closes: #5326
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20930>
 2023-02-03 14:25:19 +00:00
David Heidelberg 002707ff09 ci/lavapipe: use dxvk for the traces 
Since the job is manual, this stayed overlooked.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20875>
 2023-02-03 13:48:51 +00:00
David Heidelberg 3bc1bf7eea ci: uprev piglit (etag md5 checksumming support) 
Support for FDO etag http header.

Includes line-smooth-stipple test improvements.

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20875>
 2023-02-03 13:48:51 +00:00
Qiang Yu ed419f46aa aco: remove early_rast wait insert 
It's done in nir position export.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu f6b194b648 nir,ac/llvm,aco,radv,radeonsi: remove nir_export_vertex_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu f44872c7b6 nir,ac/llvm,aco: remove nir_export_primitive_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu aea109e25d ac/nir/ngg,radv: ms use ac_nir_export_(primitive|position|parameter) 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu 80d928c20e ac/nir/ngg: gs use ac_nir_export_(position|parameter) 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu bae5a3157f ac/nir/ngg: prepare gather_vs_outputs to be used by gs 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu 80506be31b ac/nir/ngg,radv,radeonsi: nogs use ac_nir_export_(position|parameter) 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu f084e9bbe8 ac/nir/ngg: change clipdist_neg_mask_var type to uint32 
ACO does not support 8bit ALU ops.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu d798214c7b ac/nir/ngg: fix clip dist culling mask uninitialized 
Fixes: f75452918b ("ac/nir/ngg: support clipdist culling")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu 7c41cdb81f ac/nir,radv,radeonsi: gs copy shader use ac_nir_export_(position|parameter) 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu 7308637bb4 ac/nir,radv,radeonsi: legacy vs use ac_nir_export_(position|parameter) 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:44 +00:00
Qiang Yu df8c93a9f3 radeonsi: set nr_pos_exports outside of llvm translation 
This can save an abi interface when we share position export
code with RADV.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu 048d4de5e5 radeonsi: remove the extra handling for VS/TES primitive id 
We have moved si_nir_assign_param_offsets before output lowering
pass, so there won't be primitive id store output when VS/TES here.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu 59135678cf radeonsi: update outputs written nir info 
We may remove some outputs when si_nir_kill_outputs and
ac_nir_optimize_outputs, so update the outputs written
info for output lower pass to skip manipulating these
outputs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu dcccd94faf radeonsi: clamp vertex color in legacy gs instead of gs copy shader 
gs copy shader is going to emit nir_export_amd directly so this vertex
color clamp pass which apply to nir_store_output will not work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu 601ad9e0a9 amd,radeonsi: implement nir_load_force_vrs_rates_amd in driver abi 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu 58988c3239 ac/nir: add force_vrs to ac_nir_export_position 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu daa12b1ab1 ac/nir: add ac_nir_export_parameter 
For last VGT stage to export parameter outputs.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu f823581dd4 ac/nir: add ac_nir_export_position 
Used by last VGT stage to export position related outputs.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu e9268b2c06 ac/nir: gs and nogs use ac_nir_export_primitive 
Mesh shader primitive export is left unchanged because it needs
extra changes for per primitive output export when export
primitive.

Mesh shader will use second channel of primitive export.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu 8331842258 aco: implement nir_export_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu 5fe4dd3d68 ac/llvm: implement nir_export_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Qiang Yu 5f24d58549 nir: add nir_export_amd intrinsic 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
 2023-02-03 12:27:43 +00:00
Timur Kristóf 9af3a31744 ac/nir/cull: Alway remove zero-area triangles in face culling. 
The face culling algorithm should have been disabled for
conservative overestimation because it already
(mistakenly) removed some close-to-zero area triangles.

Now that the driver disables it in that case,
let's always remove zero-area triangles.
This only costs +2 SALU instructions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20987>
 2023-02-03 09:39:54 +00:00
Timur Kristóf 3508597aa1 radv: Disable NGG culling when conservative overestimation is used. 
Even when small primitive culling is disabled, the face culling algorithm
in ac_nir_cull can delete tiny triangles when their area is almost zero.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20987>
 2023-02-03 09:39:54 +00:00
Constantine Shablya 9b3b7e5091 anv: handle ATTACHMENT_OPTIMAL layout 
Closes: #8216
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21066>
 2023-02-03 09:17:03 +00:00
Yonggang Luo b1a33789b8 util: Implement util_iround with lrintf unconditionally 
Because the place that called util_iround are always ensured
that INT_MIN <= f <= INT_MAX

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19978>
 2023-02-03 04:00:17 +00:00