88b855ccea
freedreno: Decode CP_RESOURCE_LIST
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590 >
2025-10-28 19:33:22 +00:00
1c35684814
freedreno: Add synchronization-related control registers
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590 >
2025-10-28 19:33:22 +00:00
b5f1108045
freedreno/crashdec: Add support for CP_BV_MEMPOOL
...
The BV mempool is even further cut down compared to the "small mem pool"
layout which seems to be used by a610. It also shrinks the block size to
4 chunks instead of 8. This layout happens to be shared by a702, so
abstract out the layout into a "mempool size" enum.
While we're here, fix a bug with how the mempool offset for chunks is
printed. This accounts for the test diff.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590 >
2025-10-28 19:33:22 +00:00
3f70b05784
freedreno/registers: Fix encoding fields in 64b registers
...
This was already broken for BINDLESS_BASE, but we didn't notice it
because we weren't using the builders. We have to cast fields that we OR
in, and we need to return uint64_t from the legacy field functions.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590 >
2025-10-28 19:33:22 +00:00
ba427bc274
freedreno: Expand a7xx LRZ metadata definition
...
As expected there is a second copy of the metadata for the second
buffer, and pointers to the current buffer that are updated when
flipping.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590 >
2025-10-28 19:33:22 +00:00
77b68ee78b
freedreno/a7xx: Document GRAS_LRZ_CB_CNTL
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590 >
2025-10-28 19:33:21 +00:00
efc4bb5174
freedreno: Document BV BIN_PREAMBLE usage
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590 >
2025-10-28 19:33:20 +00:00
32b646c597
nir: print in_bounds info for deref_type(_ptr_as)_array
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38110 >
2025-10-28 14:21:01 +00:00
0a6d698482
spirv: set in_bounds for ptr_as_array
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38110 >
2025-10-28 14:21:01 +00:00
0ac55b786a
spirv: don't set in_bounds for structs
...
The arr::in_bounds field was set unconditionally for every deref created
for a chain. For struct derefs, which don't have this field, this would
write to an unused memory location, which is probably why this never
caused issues.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Fixes: f19cbe98e3alyssa.rosenzweig@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38110 >
2025-10-28 14:21:01 +00:00
62f0ef3445
tu: Faster descriptor set allocator
...
memmove was slow on large number of descriptor when destroying some of
them.
util_vma_heap is perfect for the task, ANV and RADV already use it.
It also simplifies the code.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38053 >
2025-10-28 11:20:05 +00:00
562bb8b62b
v3dv: align width to 256 when using simulator
...
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37887 >
2025-10-28 11:03:55 +00:00
08e2da2379
v3d: set stride alignment when using simulator
...
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37887 >
2025-10-28 11:03:55 +00:00
d48b276acd
broadcom/simulator: add helper to get stride alignment
...
Some GPUs, like AMD, has specific stride align requirements in order to
display the content correctly.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37887 >
2025-10-28 11:03:55 +00:00
5947eae0af
v3d/simulator: create GEM BOs in GTT memory for AMD GPUs
...
As the BOs created in GPU needs to be accessible from the simulator,
create them in GTT memory, with CPU access.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37887 >
2025-10-28 11:03:55 +00:00
977d4f34dd
vc4: set stride alignment when using simulator
...
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37887 >
2025-10-28 11:03:55 +00:00
aec701d094
vc4/simulator: add helper to get stride alignment
...
Some GPUs, like AMD, require specific stride alignment in order to
display the content correctly.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37887 >
2025-10-28 11:03:54 +00:00
66d715bac3
vc4/simulator: create GEM BOs in GTT memory for AMD GPUs
...
As the BOs created in GPU needs to be accessible from the simulator,
create them in GTT memory, with CPU access.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37887 >
2025-10-28 11:03:54 +00:00
84fa5ecff6
panvk/ci: Add an ANGLE job on G925
...
Disable the max-fails feature in deqp-runner for this job, since it
aborts the run due to failures that don't occur otherwise.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38051 >
2025-10-28 10:09:28 +00:00
3e14c64b28
panvk/ci: Add a VKCTS job on G925
...
This job runs on MT8196 Rauru Chromebooks.
Also remove the old G725 expectation files, as G725 is a smaller variant
of G925.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38051 >
2025-10-28 10:09:28 +00:00
c4778f1d27
panfrost/ci: Drop redundant KERNEL_IMAGE_NAME for rock-5b
...
This was already the default value.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38051 >
2025-10-28 10:09:28 +00:00
2bec7fb8c7
ci: Update linux-firmware version to pick up more ARM firmware
...
Signed-off-by: Valentine Burley <valentine.burley@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38051 >
2025-10-28 10:09:28 +00:00
0977ca2854
radeonsi/vce: Don't check ref modification and marking flags
...
The number of operations is now correctly set to 0 when needed.
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38050 >
2025-10-28 09:43:26 +00:00
1232a7a754
frontends/va: Always reset H264 slice ref modification and marking count
...
This way the driver doesn't need to check the flag.
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38050 >
2025-10-28 09:43:26 +00:00
b6a00adb41
radeonsi/vcn: Support H264 encode pic_order_cnt_type 1
...
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38052 >
2025-10-28 09:14:24 +00:00
8c2de21090
frontends/va: Support H264 encode pic_order_cnt_type 1
...
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38052 >
2025-10-28 09:14:24 +00:00
cef8eff74d
radv/video: Override H265 SPS unaligned resolutions
...
VCN requires 64x16 alignment for HEVC. When the app requests non-aligned
resolutions, make up for it with conformance window cropping.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38061 >
2025-10-28 08:53:35 +00:00
84b6d8e0d7
radv/video: Override H265 SPS block size parameters
...
VCN only supports this set of parameters.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38061 >
2025-10-28 08:53:35 +00:00
53b9389563
winsys/amdgpu: use correct vm_timeline_point for userq creation
...
doorbell does not require va address mapping from userspace and hence
amdgpu_bo_va_op_common() function is not called and therefore doorbell
bo->vm_timeline_point is not updated. Currently to wait for all mappings
to be ready doorbell vm_timeline_point is used which is incorrect.
This patch updates vm_timeline_point to wait for all bos. The bos
can be real bo or slab bo. slab bo can be from old buffer and hence
there is a check to update vm_timeline_point to wait only if it is
new.
Reported-by: Zhang, ShanYi (Ken) <ShanYi.Zhang@amd.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38059 >
2025-10-28 07:23:43 +00:00
45affb0e53
radv: advertise VK_EXT_shader_uniform_buffer_unsized_array
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38047 >
2025-10-28 07:55:40 +01:00
66bc12a747
kk: Set drawID in root descriptor table
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38067 >
2025-10-28 01:38:34 +00:00
9be352df12
kk: Enable VK_EXT_shader_atomic_float
...
Reviewed-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38067 >
2025-10-28 01:38:34 +00:00
53de36895c
kk: enable shaderStencilExport
...
This requires a small new NIR pass to force the stencil output to be unsigned.
Reviewed-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38067 >
2025-10-28 01:38:34 +00:00
d3424de889
kk: enable shaderDrawParameters
...
Currently draw_id is always 0 since we don't support multidraw yet.
Reviewed-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38067 >
2025-10-28 01:38:34 +00:00
8c9e9555e8
kk: enable logicOp
...
Reviewed-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38067 >
2025-10-28 01:38:34 +00:00
938390c075
kk: enable dualSrcBlend
...
Reviewed-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38067 >
2025-10-28 01:38:34 +00:00
a9e0adc679
nvk: Advertise VK_KHR_maintenance10
...
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38094 >
2025-10-27 16:20:32 -04:00
268a1db7cc
nvk: Advertise the new maintenance10 format features
...
We don't actually advertise compute-only or depth-only queues right now
but nothing in the spec says you have to advertise the queues in order
to advertise the bits. Setting them now ensures we don't forget them
when compute-only or transfer-only queues get added.
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38094 >
2025-10-27 16:19:43 -04:00
0a5a456259
nvk: Switch to CmdEndRendering2KHR()
...
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38094 >
2025-10-27 16:19:43 -04:00
6e3eeb6118
nvk: Plumb attachment flags through to MSAA resolve
...
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38094 >
2025-10-27 16:19:43 -04:00
bbbf037303
vulkan/meta: Handle VkResolveImageModeInfoKHR
...
This contains resolve modes which override the format-based defaults as
well as resolve flags to allow disabling sRGB conversion.
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38094 >
2025-10-27 16:19:43 -04:00
b5d5836fd1
vulkan/meta: Handle VK_RENDERING_ATTACHMENT_RESOLVE_SKIP_TRANSFER_FUNCTION_BIT
...
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38094 >
2025-10-27 16:19:43 -04:00
127de27015
vulkan/util: Add a vk_format_srgb_to_linear() helper
...
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38094 >
2025-10-27 16:19:43 -04:00
3955787ab2
anv: implement VK_KHR_maintenance10
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38045 >
2025-10-27 19:20:09 +00:00
cf81feb660
vulkan/render_pass: handle maintenance10 resolve flags
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38045 >
2025-10-27 19:20:09 +00:00
c5740c2548
vulkan/render_pass: Add a missing sType
...
Fixes: 3a204d5cf3faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38045 >
2025-10-27 19:20:09 +00:00
2899cd84e4
vulkan/runtime: enable null pointer to vkCmdSetSampleMaskEXT()
...
For VK_KHR_maintenance10
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38045 >
2025-10-27 19:20:08 +00:00
41a8c4d37c
zink: fix mesh and task shader pipeline statistics
...
Fixes: 9d0e73335ahttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38086 >
2025-10-27 18:45:28 +00:00
c544f42a79
ir3/ra: reset merge set preferred reg when unavailable
...
When a reg's merge set has a preferred reg but is currently unavailable,
it's often preferable to reset its preferred reg and assign a new one,
as this potentially reduces the number of movs needed for the as of yet
unallocated regs.
Totals from 18278 (11.10% of 164705) affected shaders:
Instrs: 14380961 -> 14340094 (-0.28%); split: -0.58%, +0.29%
CodeSize: 28522270 -> 28460942 (-0.22%); split: -0.44%, +0.23%
NOPs: 2771602 -> 2759456 (-0.44%); split: -1.17%, +0.73%
MOVs: 589951 -> 577832 (-2.05%); split: -6.63%, +4.57%
COVs: 233094 -> 232938 (-0.07%); split: -0.11%, +0.05%
Full: 276629 -> 276632 (+0.00%); split: -0.00%, +0.00%
(ss): 364508 -> 365702 (+0.33%); split: -0.73%, +1.06%
(sy): 177032 -> 176310 (-0.41%); split: -0.98%, +0.57%
(ss)-stall: 1512210 -> 1512312 (+0.01%); split: -0.92%, +0.93%
(sy)-stall: 5783986 -> 5723012 (-1.05%); split: -1.93%, +0.88%
Preamble Instrs: 2905654 -> 2904919 (-0.03%); split: -0.09%, +0.07%
Last helper: 3397081 -> 3390054 (-0.21%); split: -0.57%, +0.36%
Last baryf: 136198 -> 136439 (+0.18%); split: -0.07%, +0.25%
Cat0: 3061954 -> 3051187 (-0.35%); split: -1.11%, +0.76%
Cat1: 874681 -> 843044 (-3.62%); split: -6.57%, +2.96%
Cat2: 5226994 -> 5226663 (-0.01%); split: -0.01%, +0.00%
Cat7: 357258 -> 359126 (+0.52%); split: -0.33%, +0.85%
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37811 >
2025-10-27 18:22:58 +00:00
f58b24467a
tu: Zero MSRTSS temporary image before creating it
...
In the dynamic rendering case, the images are allocated statically out
of the command buffer and may be reused, so we have to make they are
zeroed to match the normal tu_CreateImage() path. Otherwise we may get
garbage from previous usages of the image.
Fixes: f6c7f16322https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38032 >
2025-10-27 17:56:02 +00:00
Connor Abbott